of Microprocessors

DIGITAL-TO-ANALOG AND ANALOG-TO-DIGITAL CONVERSION 415
2 MHz CLOCK
JlIlJlSLJlrulJlnIIJlJUlllllJUlJUlrLnIlJUlJ
COUNTE R STATE 123~239F1241 ~421243124412451246~47124~24~125112521253125412551176117711781179118°11811
SAMPLE 8 HOLO HOLD i -I
SAMP ----l
'-------
START TO SAR
1'--__-'
SAR DATA BIT
_"""WiUf\:::A=.;L1:o...0 ....1-__-'~O VALID
END OF CONV
Fig. 12-33. Timing diagram for 12-bit audio ADC
approximation register operation. Total parts costs should be under $30. Of
course, a suitable filter must be added to these two circuits.
A timing diagram of the unit is shown in Fig. 12-33. A sampling
cycle starts with the 8-bit counter teaching the 240 (11110000) state, which
switches the SMP-11 into its hold mold and resets the successive approximation
register. Four counts later at 244 (11110100), the SAR is allowed to run.
Conversion is complete after 12 additional counts and the counter reloads for
the next cycle. The SAH is also switched back to sample mode to reacquire
the input signal. The host system can look at the end of conversion output
signal, which holds for the sample period minus 8 f-Lsec, to determine when
valid data is present. By inserting a l2-bit latch between the SAR and host,
the data valid time is extended to a full sample period. The counter inputs are
shown connected for a 25-ks/s sample rate (40 f-Lsec, 80 counts) but can be
reconnected for any rate from 7.8 to 80 ks/s. If both the DAC from Fig.
12-28 and this ADC are being constructed, the sample rate counter can be
shared between the two.