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Musical-Applications-of-Microprocessors-2ed-Chamberlin-H-1987

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618 MUSICAL ApPLICATIONS OF MICROPROCESSORS<br />

sine table as well as greater word length. To equal the dynamic range and<br />

noise performance <strong>of</strong> the 1024 X lO-bit sine table with a true multiplier, one<br />

would have to go to a 4,096 emry sine table with 16 bits per entry.<br />

A complete block diagram <strong>of</strong> the generator is shown in Fig. 17-18. A<br />

timing diagram for the generator is given in Fig. 17-19. Note that a<br />

pipeline register has been inserted between the sine ROM and the amplitude<br />

multiplier. The purpose is to isolate the propagation delay <strong>of</strong> the phase adder<br />

and sine ROM from the delay <strong>of</strong> the amplitude multiplier. The only side<br />

effect is that the phase memory address for harmonic N is N, whereas the<br />

amplitude memory address is N + 1. This can be avoided by inserting another<br />

pipeline register between the amplitude memory and the multiplier. However,<br />

for minimum cost the comrol computer can simply take the skew into<br />

account when writing into the memories. The harmonic accumulator adds up<br />

the 64 sine waves during a major cycle. At the end <strong>of</strong> the cycle, its content is<br />

transferred to the output register, which holds it for the entire duration <strong>of</strong><br />

the next major cycle, thus giving the DAC stable data.<br />

All timing is derived from an 8-MHz crystal clock. Two clock cycles<br />

make a minor cycle and 64 minor cycles make a major cycle. All <strong>of</strong> the clock<br />

and clear inputs to the various blocks are assumed to be positive edge<br />

triggered. The first one-quarter <strong>of</strong> each minor cycle is devoted to external<br />

access to the amplitude and phase memories and the frequency-control register.<br />

This rapid rate <strong>of</strong> access allows the generator to be connected directly to<br />

the bus <strong>of</strong> most microcomputers with no wait states or buffer memories<br />

needed. The remaining three-quarters <strong>of</strong> each minor cycle, which is about<br />

190 osee, is allowed for memory access, adder delay, ete. The parallel<br />

amplitude multiplier must therefore act in approximately 150 nsee.<br />

Rapid, glitchless updating <strong>of</strong> phase makes possible a control technique<br />

that can be used to simulate inexact tuning <strong>of</strong> the harmonics. If the comrol<br />

computer periodically increments the phase parameter <strong>of</strong> a harmonic, the<br />

I _MINOR~I<br />

CYCLE<br />

8-MHz CLOCK<br />

MINOR CYCLE CLOCK (A)<br />

MAJOR CYCLE CLOCK (B)<br />

MINOR CYCLE COUNTER<br />

________----JnL..<br />

60<br />

_<br />

EXTERNAL AOORESS SELECT (C)<br />

EXTERNAL WRITE ENABLE (D)<br />

_-'~_-' '-_---''-_--'"__,IL-lL-ll.-.-<br />

Fig. 17-19. Timing diagram for Fourier series tone generator

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