of Microprocessors

DIGITAL-TO-ANALOG AND ANALOG-TO-DIGITAL CONVERTERS 231
resistor equal to the parallel combination of all of the weighted resistors. For
reasonably high-resolution converters, this equivalent resistance is essentially
R/2.
Speed
Unlike the previous scheme, the speed of this circuit is quite good. The
only limitation on speed is the switching time of the switches and the load
capacitance at the output node where all of the resistors are tied together.
Even with a slow switching time of 1 f.Lsec, a node capacitance of 10 pF, and
an R value of 50K, the settling time for 12 bits of resolution would be 1
f.Lsec + 9 (25K X 10 pF) = 3.25 f.Lsec. With this kind of speed, the limiting
factor is often the buffer amplifier usually connected to the output. For
even higher speeds, the current output configuration (output "shorted" to
the input of a current-to-voltage converter op-amp circuit) can be used to
eliminate the 2.25-f.Lsec contribution of output capacitance.
Although the speed is high, this circuit (in fact all resistive divider
networks) is subject to glitches when moving from one level to another. The
root cause of large glitches is nonsymmetrical switching time of the analog
switches. Assume for the moment that a 3-bit DAC is moving up one step
from 011 to 100 and that the switches go from 1 to 0 faster than from 0 to 1.
The resistor network will actually see a switch state of 000 during the time
between 1-0 switching and 0-1 switching. This momentary zero state creates
a large negative glitch until the most significant switch turns on. Even if
switching times are identical, the less significant bits may be slower than the
more significant ones because they handle much lower signal currents. Unequal
switching may be largely overcome in some circuit configurations, but
small glitches can still be generated during finite switching times when a
fraction of the reference voltage is still passing through a partially off switch.
Thus, although some DAC glitching is a fact of life, a simple low-pass filter
that may even be above the audio range is usually sufficient to eliminate the
effect of glitches in synthesizer control applications.
R-2R Ladder
Figure 7-6 shows a different resistance divider network that is the basis
for most modern DACs. Although somewhat more difficult to analyze than
the weighted resistor network, the output voltages are 0.0,0.25,0.5, and
0.75 times Vre(corresponding to codes of 00, 01,10, and 11. Bits are added
by inserting a switch, series 2R resistor, and lR resistor to the next lower bit
between the MSB and LSB. Note that the resistor to ground from the LSB is
2R rather than lR. This is called a terminating resistor because it simulates
the equivalent impedance of an infinite string ofless significant bits all in the
zero state.
The advantages of this configuration are numerous. One is that only
two different values of precision resistors are needed. Although about twice