of Microprocessors

SIGNAL ROUTING 289
the equivalent collection of standard voltage-controlled modules and companion
multichannel DAC.
As mentioned earlier one strength of the fixed-patched approach is the
possibility of easy, nearly infinite expandability. This is made possible by
totally parallel buses, both digital and analog, connecting the modules together.
Proper design of the buses, however, is necessary to realize this
potential.
The usual microcomputer bus is not at all acceptable for the digital
control bus of the synthesizer. For one, its speed requirement severely limits
the length and load allowable on the bus. Also, its high-speed signals, which
flip around wildly all the time, are a source of noise that can easily get into
the audio circuitry. The solution is a bus used only for transmitting data to
the voice modules. Since the microcomputer program that will be sending
data to the modules over the bus cannot go much faster than a word every 10
to 20 /Lsec, the bus can be slowed considerably, thus allowing long lengths
and minimizing noise generation. One technique that works well for controlling
rise times is to use op-amp voltage followers for bus drivers! An LM324
quad op-amp, for example, provides nice dean ramps with a 6- to lO-/Lsec
transition time for TTL levels. Slow switching CMOS logic on the modules
themselves provides virtually no load to the bus and tolerates slow rise times
without oscillation.
Figure 8-8 shows the implementation of an example synthesizer bus.
For simplicity, the bus is capable of output only, that is, data cannot be read
back from the synthesizer modules. For maximum flexibility and expandability,
16 address lines and 16 data lines are defined. The interface between the
bus and the computer consists simply of four 8-bit output ports, or if a
16-bit processor is used, two 16-bit ports. With up to 65,536 addresses
available, an addressing standard can be defined whereby the most significant
8 bits define a particular module and the least significant 8 bits address a
function within that module allowing up to 256 modules and 256 functions
per module to be addressed.
To perform a data transfer, one merely sets up the address and data
output ports. When the last port has been written into by the microcomputer,
a pair of single-shots times out the data transfer to the synthesizer
over the next 20 p.,sec. A CMOS gate and latches on the module board
decode the register address and latch the data in response to data on the bus.
Series resistors on the CMOS inputs protect against mishaps on the bus.
Because of the slow speed of the bus and inherent noise immunity of
CMOS, several feet of open backplane wiring can be easily driven without
perceptible signal degradation. If the bus must be run some distance in a
cable, the 32 data and address lines can be individual conductors with no
special shielding. The write-enable signal, however, should be run as a
twisted pair with ground to minimize noise pickup from the other signal
lines. Combined with an overall shield, cable lengths up to 50 feet can be
easily accommodated.