of Microprocessors

Table 5-4. 68000 Instruction Set Summary
Opcode Size Source Destination Operation
ABCD B D D Binary coded decimal add source to destina-
B M M tion with extend
ADD BWL Gs D Twos complement binary add source to des-
BWL D Gm-R tination with result stored in destination
ADDA WL Gs A
ADDI BWL I Gd-A
ADDQ BWL Q3 Gd
ADDX BWL 0 0 Twos complement binary add source to des-
BWL M M tination with extend
AND BWL Gs-A 0 Logical AND source to destination
0 Gm-R
ANOI BWL I Gd-A
ANOI xx B I xx Logical AND to condition code or status
register; status register is privileged
ASL BWL Q3 0 Arithmetic shift left data register; shift count
BWL 0 0 is in source
W Gd-R Shift memory left one bit position only
ASR BWL Q3 0 Arithmetic shift right data register; shift count
BWL 0 0 is in source.
W Gd-R Shift memory right one bit position only
Bcc BW 08,16 Branch relative if condition is true
BCHG L I 0 Test the bit number specified by the source
B I Gd-R and set the zero condition according to its
L 0 0 state; then change the bit to the opposite
B 0 Gd-R state
BCLR L I D Test the bit number specified by the source
B I Gd-R and set the zero condition according to its
L 0 0 state; then clear the bit to zero
B 0 Gd-R
BSET L I 0 Test the bit number specified by the source
B I Gd-R and set the zero condition according to its
L 0 0 state; then set the bit to one
B 0 Gd-R
BSR BW 08,16 Branch relative to subroutine; 32-bit return
address pushed onto stack
BTST L I 0 Test the bit number specified by the source
B I Gd-R and set the zero condition according to its
L 0 D state
B 0 Gd-R
CHK W Gs-A 0 Destination compared against zero and content
of source; trap if less than 0 or greater
than source
CLR BWL Gd-A Clear the destination to zero
CMP BWL Gs D Subtract source from destination and set
CMPA BWL Gs A condition codes
CMPI BWL I Gd-A
CMPM BWL M+ M+
OBcc W 016 0 Continue if condition is true; if false, decrement
destination and branch relative if not
zero
OIVS W Gs-A 0 Divide 32-bit destination by 16-bit source
DIVU W Gs-A D and store 16-bit quotient and remainder in
the destination; signed and unsigned
EOR BWL 0 Gd-A Logical exclusive-or source to destination
EORI BWL I Gd-A
EORI xx B I xx Logical exclusive-or to condition codes or
status register; status register is privileged