of Microprocessors

Table 5-4. 68000 Instruction Set Summary (Cont.)
Opcode Size Source Destination Operation
RTS
SBCD
Scc
STOP
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
TAS
TRAP
TRAPV
TST
UNLK
B 0
B M
B
116
BWL Gs
BWL 0
WL Gs
BWL J
BWL Q3
BWL 0
BWL M
W
B
L
14
o
M
Gd-A
o
Gm-R
A
Gd-A
Gd
o
M
D
Gd-A
Gd-A
A
Program counter restored from the stack
Binary coded decimal subtract source from
destination with extend
Set ail bits in destination equal to specified
condition (false = 0, true = 1)
Load source into status register and stop
until interrupted, privileged
Twos complement binary subtract source
from destination with result stored in
destination
Twos complement binary subtract source
from destination with extend
Swap 16-bit halves of destination
Set negative and zero condition code according
to destination and then set bit 7 of
destination; uses special read-modifywrite
bus cycle
Generate internal interrupt to trap vector
specified by 4-bit immediate field
Generate internal interrupt if overflow condition
is set
Set condition codes according to destination
The stack pointer is loaded from the specified
address register; a long word is then
popped from the stack and loaded into the
address register
Addressing mode key:
Gs General source address, any of the coded address modes in Table 5-3.
Gd General destination address, any of the coded address modes except the immediate and relative
modes.
Gm General memory address, any of the coded address modes except register direct.
Gj General jump address, any of the coded modes except register direct, predecrement, postincrement,
and immediate.
-A Address register direct not allowed.
- R Neither address nor data register direct allowed.
- + Address register indirect postincrement not allowed.
Address register indirect predecrement not allowed.
- + Neither postincrement nor predecrement is allowed.
A Any address register.
D Any data register.
M Address register indirect addressing mode.
Mo Address register indirect with offset addressing mode.
I Any of the immediate addressing modes, length equal to operation length or a following number.
Q Quick immediate, either 3 bits (range 1-8) or 8 bits (range - 128 to + 127).
o Offset (displacement) following the instruction, either 8 or 16 bits.
RL Register list coded as a 16-bit word following the instruction. Each bit corresponds to a register
and a 1 bit means process the register.
xx Specialized source or destination as listed in instruction description.
a single 16-bit instruction. Along with arithmetic, the usual And, Or, and
Exclusive-Or operations are available with either a data register or memory as
the destination.
The 68000 maintains five condition code bits that are set after most
instructions. Four of these are Negative, Zero, Carry, and Overflow, which
are used by the conditional branch instructions. The fifth is called Extend