Operating Manual Vol 1 - ES Documentation

SMIQDigital Standard IS-95 CDMA2.12.1 Sync and Trigger SignalsA CDMA sequence with a length of 98304 chips is calculated for the generation of forward link CDMAsignals and stored in the memory of the data generator (option SMIQB11). This chip sequence can berun repetitively (TRIGGER MODE AUTO). During reverse link signal generation with channel coding, themodulation data are continuously processed in real time.Trigger signals can be used for synchronized measurements on receivers.A trigger signal can be fed via the TRIGIN input at connector PAR DATA. The chip sequence eitherstarts immediately after the active slope of the trigger signal or after a settable number of chips(TRIGGER DELAY). Retriggering (RETRIG) can be inhibited for a settable number of chips (TRIGGERINHIBIT).A trigger event can be executed manually or via the IEC/IEEE bus using EXECUTE TRIGGER. When atrigger event is executed, a trigger signal is output at the TRIGOUT 3 output of SMIQ.SMIQ also generates the following sync signals:• a 20-ms frame clock (traffic channel frame clock)• a 80/3-ms clock (short sequence rollover)• a 80-ms clock (super frame clock))• a 2-s clock (even second clock)• a PCG clock in reverse link at half rate, 1/4 rate and 1/8 rateSMIQ can output two of the four signals via pins TRIGOUT 1 and 2 of connector PAR DATA.Even second clockPeriod: 2 sec.Superframe80 msShort SequenceRoll OverShort CodePeriod80/3 ms20 msPaging Frame,Traffic Framet=0Short Code I_PN=15 *'0'Fig. 2-80CDMA sync signalsA clock synthesizer on the modulation coder generates the chip clock and a multifold chip clock in theSMIQ. All the clock signals are synchronized to the 10-MHz reference of the SMIQ. The chip clock isavailable at connector SYMBOL CLOCK and the multifold chip clock at connector BIT CLOCK. Ifrequired, the clock synthesizer in the SMIQ can be synchronized to an external chip clock which is fed inat connector SYMBOL CLOCK.The clock signal is selected in the menu via CLOCK-CLOCK SOURCE EXT.To allow for a trouble-free synchronization of the clock synthesizer first apply the external clock and setthe correct symbol rate at SMIQ. Then switch CLOCK SOURCE from INT to EXT.Note:The set symbol rate should not differ by more than 1% from the symbol rate of the externalsignal.1125.5555.03 2.133E-9