Operating Manual Vol 1 - ES Documentation

SMIQDigital Standard 3GPP W-CDMA (FDD)2Shift suspend afterevery 256-th chipcycle7 6 5 43210mod 2c t (n)+ + +2+ mod n addition7 6 5 43mod 2210b s (n)mod 4+z v (n)MapperS v (n)multiplication+ ++7 6 5 4 3 2 10a r (n)mod 43 32+ + + +3Fig. 2-99Structure of the uplink short scrambling code generatorTable 2-20Generator polynomials of uplink short scrambling code generatorsShift register 1 (binary) x 8 +x 7 +x 5 +x 4 +1Shift register 2 (binary)x 8 +x 7 +x 5 +x+1Shift register 3 (quaternary) x 8 +x 5 +3x 3 +x 2 +2x1The output sequences of the two binary shift registers are weighted with factor 2 and added to theoutput sequence of the quaternary shift register (Modulo 4 addition). The resulting quaternary outputsequence is mapped into the binary complex level by the mapper block.For initialization of the three 8-bit shift registers (in a modified way) the binary form of the 24-bit short SCnumber n is used, for details see section 4.3.2.3 in [2].Table 2-21Mapping of the quaternary output sequence into the binary IQ levelzv(n) Sv(n)0 +1 + j11 -1 + j12 -1 - j13 +1 - j1c) Preamble scrambling code generatorWhen generating the preambles of the PRACH and PCPCH a special SC is used. It is based on thelong SC described under a), however only the I component is taken and subsequently a pointer (e j(PI/4 +PI/4 * k) , k=0 to 4095) modulated upon it.Modification of the long and short scrambling code output sequenceThe scrambling code sequence of the Q component is modified as standard to reduce the crest factor ofthe signal. Zero-crossings can then be avoided for every second chip using this method. (This method isoften called HPSK).For details see [2], section 4.3.2.1. The SMIQ uses a decimation factor of 2.1125.5555.03 2.173E-9