Operating Manual Vol 1 - ES Documentation

Digital Standard 3GPP W-CDMA (FDD)SMIQ17161514131211109876543210IQ1716151413121110987654321 0Fig. 2-98Structure of the downlink scrambling code generatorThe shift registers are initialized by loading shift register 1 with "0 to 01" and shift register 2 with all "1".In addition, shift register 1 is run forward by n cycles, n being the scrambling code number or in short the"scrambling code" (SC).After a cycle time of one radio frame the generators are reset, i.e. the above initialization is carried outagain.2. Uplink scrambling code generatorIn the uplink, distinction is made between two modes of the SC. There is on the one hand the long SCwhich can be used for all types of channel. On the other hand, there is the short SC which can be usedfor all channels except PRACH and PCPCH as an alternative to the long SC.a) Uplink long scrambling code generatorThe code generator of the long SC in the uplink has basically the same structure as the SC in thedownlink. However, the generator polynomials of the shift registers and the type of initialization differ.Table 2-19Generator polynomials of uplink long scrambling code generatorsShift register 1 x 25 +x 3 +1Shift register 2x 25 +x 3 +x 2 +x+1The shift registers are initialized by assigning 1 to bit number 24 in shift register 1 and the binary form ofthe scrambling code number n to bits 23 to 0. Shift register 2 is loaded with all "1".The readout positions for the Q component are such that they correspond to an IQ offset of 16.777.232cycles.After a cycle time of one radio frame the generators are reset, i.e. the above initialization is carried outagain.b) Uplink short scrambling code generatorThe code generator of the short SC in the uplink comprises altogether 3 coupled shift registers.1125.5555.03 2.172E-9