Operating Manual Vol 1 - ES Documentation

SMIQDigital Standard 3GPP W-CDMA (FDD)2.14.1.1 System ComponentsScrambling CodeGenerator IScrambling CodeGenerator QChannelization CodeGeneratorChannelization CodeNumberScrambling Code InitSCiScrambling Code InitSCqUplink Modifier ("HPSK")SCq'CHSlot and Frame BuilderDiCiScrambling UnitSiPower ControlSummationData SourceData OffsetDemultiplexerDqCqSqChannel PowerCh. 0FilteringCh. NFig. 2-97Components of 3GPP W-CDMA transmission systemThe individual functional blocks are described below in detail.Scrambling code generatorThe scrambling code generator (formerly long code generator) is used to scramble the chip sequenceas a function of the transmitter. The structure and initialization rule of the generator differ depending onthe link direction and the mode (long or short).1. Downlink scrambling code generatorThis generator consists of a pair of shift registers from which the binary sequences for in-phase andquadrature components of the scrambling code are determined. Fig. 2-98 shows that the I componentresults from an EXOR link of the LSB outputs whereas for the Q component the register contents arefirst output masked and then EXORed.Note: As an alternative, the Q component can be determined via a second pair of registers withthe same structure, which idle for a certain number of cycles before the scrambling codebits are output. This I/Q offset is 131.072 in the downlink and 16.777.232 in the similarlydesigned uplink long scrambling code generator. For reasons of simplicity, theimplementation shown in Fig. 2-98 is the better choice.Generator polynomials of downlink scrambling code generatorsShift register 1 x 18 +x 7 +1Shift register 2 x 18 +x 10 +x 7 +x 5 +11125.5555.03 2.171E-9