Operating Manual Vol 1 - ES Documentation

Bit Error Rate TestSMIQ2.23.2.4 Possible BLER Measurement Problems and SolutionsFault Possible cause Fault description/remedyBLERmeasurementdoes notsynchronizeNo signals received fromDUT or the signal level is notcorrect.A wrong clock edge is used,which violates setup or holdtimes.Incorrect polarity of datasignal (or DATA ENABLEsignal). Check activity at BLER measurement inputs in the display.A status display (Clock, Data, Sync) signals activity on the respectiveline. Check the bit clock signal, the data signal and the DATA ENABLEsignal, if any, on an oscilloscope.The fault may also be caused by reflections on the clock line, whichclock the data signal twice into the BLER measurement, e.g. if lines arenot terminated. The SMIQ input is not terminated.In this case the CRC tester cannot synchronize.No clock receivedfrom DUTWhen testing RFcomponents, clock recoverymay not be available. Anexternal clock is howeverrequired for clocking the dataduring the BLERmeasurement.The bit clock at the PAR DATA connector of the SMIQ may be usedinstead of a clock recovery circuit. This is possible if DGEN (SMIQB11)is used as a data source. However, this bit clock is not available with allmodulation types. Also, the delay between data and clock has to betaken into account.Measured BLERtoo highThe data is switched with thewrong clock edge and/or theeye pattern of the data is notoptimally met. Check the clock/data relationship by means of an oscilloscope andoptimize the timing.1125.5555.03 2.382 E-9