Intel® Architecture Instruction Set Extensions Programming Reference

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$Intel® Math Kernel Library (Intel® MKL) 11.0 Release Notes$

$Intel® Math Kernel Library 11.0 Support for Intel® Xeon Phi ...$

DEST[255:248] SaturateSignedWordToUnsignedByte (SRC2[255:240]); Intel C/C++ Compiler Intrinsic Equivalent (V)PACKUSWB: __m128i _mm_packus_epi16(__m128i m1, __m128i m2); VPACKUSWB: __m256i _mm256_packus_epi16(__m256i m1, __m256i m2); SIMD Floating-Point Exceptions None Other Exceptions See Exceptions Type 4 INSTRUCTION SET REFERENCE Ref. # 319433-014 5-25
INSTRUCTION SET REFERENCE PADDB/PADDW/PADDD/PADDQ — Add Packed Integers Opcode/ <strong>Instruction</strong> Op/ En 64/32 -bit Mode CPUID Feature Flag Description 66 0F FC /r A V/V SSE2 Add packed byte integers from xmm2/m128 and xmm1. PADDB xmm1, xmm2/m128 66 0F FD /r A V/V SSE2 Add packed word integers from xmm2/m128 and xmm1. PADDW xmm1, xmm2/m128 66 0F FE /r A V/V SSE2 Add packed doubleword integers from xmm2/m128 and xmm1. PADDD xmm1, xmm2/m128 66 0F D4/r A V/V SSE2 Add packed quadword integers from xmm2/m128 and xmm1. PADDQ xmm1, xmm2/m128 VEX.NDS.128.66.0F.WIG FC /r B V/V AVX Add packed byte integers from xmm2, and xmm3/m128 and store in xmm1. VPADDB xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG FD /r B V/V AVX Add packed word integers from xmm2, xmm3/m128 and store in xmm1. VPADDW xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG FE /r B V/V AVX Add packed doubleword integers from xmm2, xmm3/m128 and store in xmm1. VPADDD xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG D4 /r B V/V AVX Add packed quadword integers from xmm2, xmm3/m128 and store in xmm1. VPADDQ xmm1, xmm2, xmm3/m128 VEX.NDS.256.66.0F.WIG FC /r B V/V AVX2 Add packed byte integers from ymm2, and ymm3/m256 and store in ymm1. VPADDB ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG FD /r B V/V AVX2 Add packed word integers from ymm2, ymm3/m256 and store in ymm1. VPADDW ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG FE /r B V/V AVX2 Add packed doubleword integers from ymm2, ymm3/m256 and store in ymm1. VPADDD ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG D4 /r B V/V AVX2 Add packed quadword integers from ymm2, ymm3/m256 and store in ymm1. VPADDQ ymm1, ymm2, ymm3/m256 5-26 Ref. # 319433-014
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Intel® Architecture Instruction Se
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CONTENTS CHAPTER 1 INTEL® ADVANCED
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PANDN — Logical AND NOT . . . . .
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BZHI — Zero High Bits Starting wi
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TABLES 2-1 Rounding behavior of Zer
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FIGURES Figure 2-1. General Procedu
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INTEL® ADVANCED VECTOR EXTENSIONS
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APPLICATION PROGRAMMING MODEL Prior
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APPLICATION PROGRAMMING MODEL } and
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APPLICATION PROGRAMMING MODEL Scala
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APPLICATION PROGRAMMING MODEL x (mu
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APPLICATION PROGRAMMING MODEL Instr
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APPLICATION PROGRAMMING MODEL Table
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APPLICATION PROGRAMMING MODEL Excep
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APPLICATION PROGRAMMING MODEL 2.7.2
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APPLICATION PROGRAMMING MODEL EAX 3
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Page 59 and 60: APPLICATION PROGRAMMING MODEL Table
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Page 63 and 64: APPLICATION PROGRAMMING MODEL How B
Page 65 and 66: APPLICATION PROGRAMMING MODEL
Page 67 and 68: APPLICATION PROGRAMMING MODEL EAX[1
Page 69 and 70: APPLICATION PROGRAMMING MODEL EBX
Page 71 and 72: SYSTEM PROGRAMMING MODEL • Verify
Page 73 and 74: SYSTEM PROGRAMMING MODEL The proces
Page 75 and 76: SYSTEM PROGRAMMING MODEL 3.3 RESET
Page 77 and 78: INSTRUCTION FORMAT 4.1.1 VEX and th
Page 79 and 80: INSTRUCTION FORMAT (Bit Position) 7
Page 81 and 82: INSTRUCTION FORMAT The VEX.vvvv fie
Page 83 and 84: INSTRUCTION FORMAT 4.1.8 The Third
Page 85 and 86: INSTRUCTION FORMAT NOTES: 1. If Mod
Page 87 and 88: INSTRUCTION SET REFERENCE (V)ADDSD
Page 89 and 90: INSTRUCTION SET REFERENCE register
Page 91 and 92: INSTRUCTION SET REFERENCE MPSADBW
Page 93 and 94: INSTRUCTION SET REFERENCE SRC2_BYTE
Page 95 and 96: INSTRUCTION SET REFERENCE VMPSADBW
Page 97 and 98: INSTRUCTION SET REFERENCE DEST[79:6
Page 99 and 100: INSTRUCTION SET REFERENCE Operation
Page 101 and 102: INSTRUCTION SET REFERENCE PACKSSWB/
Page 105 and 106: INSTRUCTION SET REFERENCE PACKUSDW
Page 107 and 108: INSTRUCTION SET REFERENCE TMP[239:2
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Page 113 and 114: INSTRUCTION SET REFERENCE PADDQ (Le
Page 115 and 116: INSTRUCTION SET REFERENCE PADDSB/PA
Page 117 and 118: INSTRUCTION SET REFERENCE PADDUSB/P
Page 119 and 120: INSTRUCTION SET REFERENCE PALIGNR
Page 121 and 122: INSTRUCTION SET REFERENCE PAND —
Page 123 and 124: INSTRUCTION SET REFERENCE PANDN —
Page 125 and 126: INSTRUCTION SET REFERENCE PAVGB/PAV
Page 127 and 128: INSTRUCTION SET REFERENCE PBLENDVB
Page 129 and 130: INSTRUCTION SET REFERENCE IF (MASK[
Page 131 and 132: INSTRUCTION SET REFERENCE PBLENDW
Page 133 and 134: INSTRUCTION SET REFERENCE ELSE DEST
Page 135 and 136: INSTRUCTION SET REFERENCE Descripti
Page 137 and 138: INSTRUCTION SET REFERENCE PCMPEQQ (
Page 139 and 140: INSTRUCTION SET REFERENCE Descripti
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Page 145 and 146: INSTRUCTION SET REFERENCE PHADDSW
Page 147 and 148: INSTRUCTION SET REFERENCE PHSUBW/PH
Page 153 and 154: INSTRUCTION SET REFERENCE PMADDUBSW
Page 155 and 156: INSTRUCTION SET REFERENCE VPMADDWD
Page 157 and 158: INSTRUCTION SET REFERENCE VEX.128 e
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INSTRUCTION SET REFERENCE VEX.256 e
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INSTRUCTION SET REFERENCE DEST[255:
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INSTRUCTION SET REFERENCE VPMINUD (
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INSTRUCTION SET REFERENCE PMOVMSKB
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INSTRUCTION SET REFERENCE Opcode/ I
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INSTRUCTION SET REFERENCE VPMOVSXWQ
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INSTRUCTION SET REFERENCE PMOVZX
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INSTRUCTION SET REFERENCE Packed_Ze
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE Operation
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INSTRUCTION SET REFERENCE temp13[31
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INSTRUCTION SET REFERENCE PMULHUW
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE DEST[15:0
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INSTRUCTION SET REFERENCE PMULLW/PM
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INSTRUCTION SET REFERENCE Temp10[31
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INSTRUCTION SET REFERENCE PMULUDQ
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INSTRUCTION SET REFERENCE POR — B
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INSTRUCTION SET REFERENCE PSADBW
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INSTRUCTION SET REFERENCE PSHUFB
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INSTRUCTION SET REFERENCE PSHUFD
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INSTRUCTION SET REFERENCE PSHUFHW
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INSTRUCTION SET REFERENCE PSHUFLW
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INSTRUCTION SET REFERENCE PSIGNB/PS
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INSTRUCTION SET REFERENCE DEST[255.
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INSTRUCTION SET REFERENCE PSLLDQ
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INSTRUCTION SET REFERENCE PSLLW/PSL
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INSTRUCTION SET REFERENCE PSLLD (xm
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INSTRUCTION SET REFERENCE PSRAW/PSR
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INSTRUCTION SET REFERENCE COUNT 31
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INSTRUCTION SET REFERENCE PSRLDQ
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INSTRUCTION SET REFERENCE PSRLW/PSR
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INSTRUCTION SET REFERENCE FI; DEST[
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INSTRUCTION SET REFERENCE VPSRLQ (x
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE PSUBSB/PS
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INSTRUCTION SET REFERENCE PSUBUSB/P
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INSTRUCTION SET REFERENCE PUNPCKHBW
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INSTRUCTION SET REFERENCE DEST[95:8
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INSTRUCTION SET REFERENCE VPUNPCKHW
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INSTRUCTION SET REFERENCE Instructi
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INSTRUCTION SET REFERENCE INTERLEAV
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INSTRUCTION SET REFERENCE VPUNPCKLD
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INSTRUCTION SET REFERENCE SIMD Floa
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INSTRUCTION SET REFERENCE VBROADCAS
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE VPBLENDD
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INSTRUCTION SET REFERENCE VPBROADCA
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INSTRUCTION SET REFERENCE VPERMPD
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INSTRUCTION SET REFERENCE VPERMQ
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INSTRUCTION SET REFERENCE VINSERTI1
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INSTRUCTION SET REFERENCE The secon
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INSTRUCTION SET REFERENCE VPSLLVD/V
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE VPSRAVD (
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INSTRUCTION SET REFERENCE VPSRLVD (
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE This page
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INSTRUCTION SET REFERENCE - FMA VFM
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INSTRUCTION SET REFERENCE - FMA For
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INSTRUCTION SET REFERENCE - FMA sou
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INSTRUCTION SET REFERENCE - FMA Int
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA } I
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INSTRUCTION SET REFERENCE - FMA ope
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INSTRUCTION SET REFERENCE - FMA VFN
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA Thi
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INSTRUCTION SET REFERENCE - VEX-ENC
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INTEL® TRANSACTIONAL SYNCHRONIZATI
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ADDITIONAL NEW INSTRUCTIONS -------
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ADDITIONAL NEW INSTRUCTIONS • If
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ADDITIONAL NEW INSTRUCTIONS ADCX
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ADDITIONAL NEW INSTRUCTIONS ADOX
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ADDITIONAL NEW INSTRUCTIONS Compati
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ADDITIONAL NEW INSTRUCTIONS Flags A
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ADDITIONAL NEW INSTRUCTIONS STAC—
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OPCODE MAP D The reg field of the M
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OPCODE MAP • A ModR/M byte is req
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OPCODE MAP A.2.5 Superscripts Utili
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OPCODE MAP Table A-2. One-byte Opco
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OPCODE MAP 0 1 2 3 4 5 6 7 Table A-
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OPCODE MAP 8 9 A B C D E F Table A-
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OPCODE MAP 0 Table A-4. Three-byte
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OPCODE MAP 0 66 1 66 2 66 3 4 66 5
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OPCODE MAP A.4 OPCODE EXTENSIONS FO
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OPCODE MAP Opcode Group Mod 7,6 pfx
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OPCODE MAP Table A-8 shows the map
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OPCODE MAP Table A-20 shows the opc
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OPCODE MAP This page was intentiona
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INSTRUCTION SUMMARY VEX.256 Encodin
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INSTRUCTION SUMMARY Note 3: It is e
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INSTRUCTION SUMMARY Table B-2. Prom
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INSTRUCTION SUMMARY Table B-3. VEX-
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INSTRUCTION SUMMARY Opcode Instruct
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SSE extensions flag . . . . . . . .
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SSE extensions CPUID flag . . . . .
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I-6 Ref. # 319433-014
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Intel® Architecture Instruction Set Extensions Programming Reference

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