Intel® Architecture Instruction Set Extensions Programming Reference

PMAXUB/PMAXUW/PMAXUD — Maximum of Packed Unsigned Integers
Opcode/
Instruction
Description
Op/
En
64/32
-bit
Mode
CPUID
Feature
Flag
Description
Instruction Operand Encoding
INSTRUCTION SET REFERENCE
66 0F DE /r A V/V SSE2 Compare packed unsigned byte integers in xmm1 and
xmm2/m128 and store packed maximum values in xmm1.
PMAXUB xmm1, xmm2/m128
66 0F 38 3E/r A V/V SSE4_1 Compare packed unsigned word integers in xmm2/m128 and
xmm1 and stores maximum packed values in xmm1.
PMAXUW xmm1, xmm2/m128
66 0F 38 3F /r A V/V SSE4_1 Compare packed unsigned dword integers in xmm1 and
xmm2/m128 and store packed maximum values in xmm1.
PMAXUD xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG DE /r B V/V AVX Compare packed unsigned byte integers in xmm2 and
xmm3/m128 and store packed maximum values in xmm1.
VPMAXUB xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F38.WIG 3E /r B V/V AVX Compare packed unsigned word integers in xmm3/m128 and
xmm2 and store maximum packed values in xmm1.
VPMAXUW xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F38.WIG 3F /r B V/V AVX Compare packed unsigned dword integers in xmm2 and
xmm3/m128 and store packed maximum values in xmm1.
VPMAXUD xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F.WIG DE /r B V/V AVX2 Compare packed unsigned byte integers in ymm2 and
ymm3/m256 and store packed maximum values in ymm1.
VPMAXUB ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F38.WIG 3E /r B V/V AVX2 Compare packed unsigned word integers in ymm3/m256 and
ymm2 and store maximum packed values in ymm1.
VPMAXUW ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F38.WIG 3F /r B V/V AVX2 Compare packed unsigned dword integers in ymm2 and
ymm3/m256 and store packed maximum values in ymm1.
VPMAXUD ymm1, ymm2,
ymm3/m256
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
B ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA
Performs a SIMD compare of the packed unsigned byte, word, or dword integers in the second source operand and
the first source operand and returns the maximum value for each pair of integers to the destination operand.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (255:128) of the corresponding YMM destination
register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (255:128) of the corresponding YMM register are
zeroed.
Ref. # 319433-014 5-75