Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS
PEXT — Parallel Bits Extract
Opcode/Instruction Op/
En
Description
Instruction Operand Encoding
PEXT uses a mask in the second source operand (the third operand) to transfer either contiguous or non-contiguous
bits in the first source operand (the second operand) to contiguous low order bit positions in the destination
(the first operand). For each bit set in the MASK, PEXT extracts the corresponding bits from the first source operand
and writes them into contiguous lower bits of destination operand. The remaining upper bits of destination are
zeroed.
Figure 7-2. PEXT Example
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
TEMP ← SRC1;
MASK ← SRC2;
DEST ← 0 ;
m← 0, k← 0;
DO WHILE m< OperandSize
IF MASK[ m] = 1 THEN
DEST[ k] ← TEMP[ m];
k ← k+ 1;
64/32
-bit
Mode
CPUID
Feature
Flag
Description
VEX.NDS.LZ.F3.0F38.W0 F5 /r A V/V BMI2 Parallel extract of bits from r32b using mask in r/m32, result is written
to r32a.
PEXT r32a, r32b, r/m32
VEX.NDS.LZ.F3.0F38.W1 F5 /r A V/N.E. BMI2 Parallel extract of bits from r64b using mask in r/m64, result is written
to r64a.
PEXT r64a, r64b, r/m64
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) NA
SRC1
SRC2
(mask)
DEST
S31 S30 S29 S28 S27 S7 S6 S5 S4 S3 S2 S1 S0 0
0
bit 31
0
0
0
0
1
0
0
0
7-16 Ref. # 319433-014
1
0
0
0
1
0
0
0
0
1
S28 S7 0
S 5
0
S 2
bit 0