Intel® Architecture Instruction Set Extensions Programming Reference

Operation
255 224 192
Src2
Src1
255
Destination
127 96 64
Src2
Src1
127
Destination
VMPSADBW (VEX.256 encoded version)
SRC2_OFFSET imm8[1:0]*32
SRC1_OFFSET imm8[2]*32
SRC1_BYTE0 SRC1[SRC1_OFFSET+7:SRC1_OFFSET]
SRC1_BYTE1 SRC1[SRC1_OFFSET+15:SRC1_OFFSET+8]
SRC1_BYTE2 SRC1[SRC1_OFFSET+23:SRC1_OFFSET+16]
SRC1_BYTE3 SRC1[SRC1_OFFSET+31:SRC1_OFFSET+24]
SRC1_BYTE4 SRC1[SRC1_OFFSET+39:SRC1_OFFSET+32]
SRC1_BYTE5 SRC1[SRC1_OFFSET+47:SRC1_OFFSET+40]
SRC1_BYTE6 SRC1[SRC1_OFFSET+55:SRC1_OFFSET+48]
SRC1_BYTE7 SRC1[SRC1_OFFSET+63:SRC1_OFFSET+56]
SRC1_BYTE8 SRC1[SRC1_OFFSET+71:SRC1_OFFSET+64]
SRC1_BYTE9 SRC1[SRC1_OFFSET+79:SRC1_OFFSET+72]
SRC1_BYTE10 SRC1[SRC1_OFFSET+87:SRC1_OFFSET+80]
Abs. Diff.
Figure 5-1. VMPSADBW Operation
Imm[4:3]*32+128
Abs. Diff.
INSTRUCTION SET REFERENCE
Ref. # 319433-014 5-7
Sum
Imm[5]*32+128
144
Imm[1:0]*32
Sum
Imm[2]*32
16
128
128
0
0