Intel® Architecture Instruction Set Extensions Programming Reference

VEX.m-mmmm
Table 4-3. VEX.m-mmmm Interpretation
Implied Leading Opcode Bytes
00000B Reserved
00001B 0F
00010B 0F 38
00011B 0F 3A
00100-11111B Reserved
(2-byte VEX) 0F
VEX.m-mmmm is only available on the 3-byte VEX. The 2-byte VEX implies a leading 0Fh opcode byte.
4.1.5.2 2-byte VEX byte 1, bit[2], and 3-byte VEX byte 2, bit [2]- “L”
INSTRUCTION FORMAT
The vector length field, VEX.L, is encoded in bit[2] of either the second byte of 2-byte VEX, or the third byte of 3byte
VEX. If “VEX.L = 1”, it indicates 256-bit vector operation. “VEX.L = 0” indicates scalar and 128-bit vector operations.
The instruction VZEROUPPER is a special case that is encoded with VEX.L = 0, although its operation zero’s bits
255:128 of all YMM registers accessible in the current operating mode.
See the following table.
Table 4-4. VEX.L Interpretation
VEX.L Vector Length
0 128-bit (or 32/64-bit scalar)
1 256-bit
4.1.5.3 2-byte VEX byte 1, bits[1:0], and 3-byte VEX byte 2, bits [1:0]- “pp”
Up to one implied prefix is encoded by bits[1:0] of either the 2-byte VEX byte 1 or the 3-byte VEX byte 2. The prefix
behaves as if it was encoded prior to VEX, but after all other encoded prefixes.
See the following table.
pp
Table 4-5. VEX.pp Interpretation
Implies this prefix after other prefixes but before VEX
00B None
01B 66
10B F3
11B F2
4.1.6 The Opcode Byte
One (and only one) opcode byte follows the 2 or 3 byte VEX. Legal opcodes are specified in Appendix B, in color.
Any instruction that uses illegal opcode will #UD.
4.1.7 The MODRM, SIB, and Displacement Bytes
The encodings are unchanged but the interpretation of reg_field or rm_field differs (see above).
Ref. # 319433-014 4-7