Intel® Architecture Instruction Set Extensions Programming Reference

B.1 AVX INSTRUCTIONS
INSTRUCTION SUMMARY
APPENDIX B
INSTRUCTION SUMMARY
In AVX, most SSE/SSE2/SSE3/SSSE3/SSE4 Instructions have been promoted to support VEX.128 encodings
which, for non-memory-store versions implies support for zeroing upper bits of YMM registers. Table B-1 summarizes
the promotion status for existing instructions. The column “VEX.256” indicates whether 256-bit vector form
of the instruction using the VEX.256 prefix encoding is supported. The column “VEX.128” indicates whether the
instruction using VEX.128 prefix encoding is supported.
VEX.256
Encoding
VEX.128
Encoding
Table B-1. Promoted SSE/SSE2/SSE3/SSSE3/SSE4 Instructions in AVX
Group Instruction If No, Reason?
yes yes YY 0F 1X MOVUPS
no yes MOVSS scalar
yes yes MOVUPD
no yes MOVSD scalar
no yes MOVLPS Note 1
no yes MOVLPD Note 1
no yes MOVLHPS Redundant with VPERMILPS
yes yes MOVDDUP
yes yes MOVSLDUP
yes yes UNPCKLPS
yes yes UNPCKLPD
yes yes UNPCKHPS
yes yes UNPCKHPD
no yes MOVHPS Note 1
no yes MOVHPD Note 1
no yes MOVHLPS Redundant with VPERMILPS
yes yes MOVAPS
yes yes MOVSHDUP
yes yes MOVAPD
no no CVTPI2PS MMX
no yes CVTSI2SS scalar
no no CVTPI2PD MMX
no yes CVTSI2SD scalar
yes yes MOVNTPS
yes yes MOVNTPD
no no CVTTPS2PI MMX
no yes CVTTSS2SI scalar
no no CVTTPD2PI MMX
Ref. # 319433-014 B-1