Intel® Architecture Instruction Set Extensions Programming Reference

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$Intel® Math Kernel Library (Intel® MKL) 11.0 Release Notes$

$Intel® Math Kernel Library 11.0 Support for Intel® Xeon Phi ...$

DEST[63:32] SignExtend(SRC[31:16]); DEST[95:64] SignExtend(SRC[47:32]); DEST[127:96] SignExtend(SRC[63:48]); Packed_Sign_Extend_WORD_to_QWORD(DEST, SRC) DEST[63:0] SignExtend(SRC[15:0]); DEST[127:64] SignExtend(SRC[31:16]); Packed_Sign_Extend_DWORD_to_QWORD(DEST, SRC) DEST[63:0] SignExtend(SRC[31:0]); DEST[127:64] SignExtend(SRC[63:32]); VPMOVSXBW (VEX.256 encoded version) Packed_Sign_Extend_BYTE_to_WORD(DEST[127:0], SRC[63:0]) Packed_Sign_Extend_BYTE_to_WORD(DEST[255:128], SRC[127:64]) VPMOVSXBD (VEX.256 encoded version) Packed_Sign_Extend_BYTE_to_DWORD(DEST[127:0], SRC[31:0]) Packed_Sign_Extend_BYTE_to_DWORD(DEST[255:128], SRC[63:32]) VPMOVSXBQ (VEX.256 encoded version) Packed_Sign_Extend_BYTE_to_QWORD(DEST[127:0], SRC[15:0]) Packed_Sign_Extend_BYTE_to_QWORD(DEST[255:128], SRC[31:16]) VPMOVSXWD (VEX.256 encoded version) Packed_Sign_Extend_WORD_to_DWORD(DEST[127:0], SRC[63:0]) Packed_Sign_Extend_WORD_to_DWORD(DEST[255:128], SRC[127:64]) VPMOVSXWQ (VEX.256 encoded version) Packed_Sign_Extend_WORD_to_QWORD(DEST[127:0], SRC[31:0]) Packed_Sign_Extend_WORD_to_QWORD(DEST[255:128], SRC[63:32]) VPMOVSXDQ (VEX.256 encoded version) Packed_Sign_Extend_DWORD_to_QWORD(DEST[127:0], SRC[63:0]) Packed_Sign_Extend_DWORD_to_QWORD(DEST[255:128], SRC[127:64]) VPMOVSXBW (VEX.128 encoded version) Packed_Sign_Extend_BYTE_to_WORDDEST[127:0], SRC[127:0]() DEST[VLMAX:128] 0 VPMOVSXBD (VEX.128 encoded version) Packed_Sign_Extend_BYTE_to_DWORD(DEST[127:0], SRC[127:0]) DEST[VLMAX:128] 0 VPMOVSXBQ (VEX.128 encoded version) Packed_Sign_Extend_BYTE_to_QWORD(DEST[127:0], SRC[127:0]) DEST[VLMAX:128] 0 VPMOVSXWD (VEX.128 encoded version) Packed_Sign_Extend_WORD_to_DWORD(DEST[127:0], SRC[127:0]) DEST[VLMAX:128] 0 INSTRUCTION SET REFERENCE Ref. # 319433-014 5-91
INSTRUCTION SET REFERENCE VPMOVSXWQ (VEX.128 encoded version) Packed_Sign_Extend_WORD_to_QWORD(DEST[127:0], SRC[127:0]) DEST[VLMAX:128] 0 VPMOVSXDQ (VEX.128 encoded version) Packed_Sign_Extend_DWORD_to_QWORD(DEST[127:0], SRC[127:0]) DEST[VLMAX:128] 0 PMOVSXBW Packed_Sign_Extend_BYTE_to_WORD(DEST[127:0], SRC[127:0]) DEST[VLMAX:128] (Unmodified) PMOVSXBD Packed_Sign_Extend_BYTE_to_DWORD(DEST[127:0], SRC[127:0]) DEST[VLMAX:128] (Unmodified) PMOVSXBQ Packed_Sign_Extend_BYTE_to_QWORD(DEST[127:0], SRC[127:0]) DEST[VLMAX:128] (Unmodified) PMOVSXWD Packed_Sign_Extend_WORD_to_DWORD(DEST[127:0], SRC[127:0]) DEST[VLMAX:128] (Unmodified) PMOVSXWQ Packed_Sign_Extend_WORD_to_QWORD(DEST[127:0], SRC[127:0]) DEST[VLMAX:128] (Unmodified) PMOVSXDQ Packed_Sign_Extend_DWORD_to_QWORD(DEST[127:0], SRC[127:0]) DEST[VLMAX:128] (Unmodified) Intel C/C++ Compiler Intrinsic Equivalent (V)PMOVSXBW: __m128i _mm_cvtepi8_epi16 ( __m128i a); (V)PMOVSXBD: __m128i _mm_cvtepi8_epi32 ( __m128i a); (V)PMOVSXBQ: __m128i _mm_cvtepi8_epi64 ( __m128i a); (V)PMOVSXWD: __m128i _mm_cvtepi16_epi32 ( __m128i a); (V)PMOVSXWQ: __m128i _mm_cvtepi16_epi64 ( __m128i a); (V)PMOVSXDQ: __m128i _mm_cvtepi32_epi64 ( __m128i a); VPMOVSXBW: __m256i _mm256_cvtepi8_epi16 ( __m128i a); VPMOVSXBD: __m256i _mm256_cvtepi8_epi32 ( __m128i a); VPMOVSXBQ: __m256i _mm256_cvtepi8_epi64 ( __m128i a); VPMOVSXWD: __m256i _mm256_cvtepi16_epi32 ( __m128i a); VPMOVSXWQ: __m256i _mm256_cvtepi16_epi64 ( __m128i a); VPMOVSXDQ: __m256i _mm256_cvtepi32_epi64 ( __m128i a); 5-92 Ref. # 319433-014
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Intel® Architecture Instruction Se
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CONTENTS CHAPTER 1 INTEL® ADVANCED
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PANDN — Logical AND NOT . . . . .
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BZHI — Zero High Bits Starting wi
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TABLES 2-1 Rounding behavior of Zer
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FIGURES Figure 2-1. General Procedu
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INTEL® ADVANCED VECTOR EXTENSIONS
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APPLICATION PROGRAMMING MODEL Prior
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APPLICATION PROGRAMMING MODEL } and
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APPLICATION PROGRAMMING MODEL Scala
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APPLICATION PROGRAMMING MODEL x (mu
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APPLICATION PROGRAMMING MODEL Instr
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APPLICATION PROGRAMMING MODEL Table
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APPLICATION PROGRAMMING MODEL Excep
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APPLICATION PROGRAMMING MODEL 2.7.2
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APPLICATION PROGRAMMING MODEL EAX 3
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APPLICATION PROGRAMMING MODEL • T
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APPLICATION PROGRAMMING MODEL How B
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APPLICATION PROGRAMMING MODEL
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APPLICATION PROGRAMMING MODEL EAX[1
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APPLICATION PROGRAMMING MODEL EBX
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SYSTEM PROGRAMMING MODEL • Verify
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SYSTEM PROGRAMMING MODEL The proces
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SYSTEM PROGRAMMING MODEL 3.3 RESET
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INSTRUCTION FORMAT 4.1.1 VEX and th
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INSTRUCTION FORMAT (Bit Position) 7
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INSTRUCTION FORMAT The VEX.vvvv fie
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INSTRUCTION FORMAT 4.1.8 The Third
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INSTRUCTION FORMAT NOTES: 1. If Mod
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INSTRUCTION SET REFERENCE (V)ADDSD
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INSTRUCTION SET REFERENCE register
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INSTRUCTION SET REFERENCE MPSADBW
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INSTRUCTION SET REFERENCE SRC2_BYTE
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INSTRUCTION SET REFERENCE VMPSADBW
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INSTRUCTION SET REFERENCE DEST[79:6
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INSTRUCTION SET REFERENCE Operation
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INSTRUCTION SET REFERENCE PACKSSWB/
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INSTRUCTION SET REFERENCE PACKUSDW
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INSTRUCTION SET REFERENCE TMP[239:2
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INSTRUCTION SET REFERENCE DEST[119:
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INSTRUCTION SET REFERENCE PADDB/PAD
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INSTRUCTION SET REFERENCE PADDQ (Le
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INSTRUCTION SET REFERENCE PADDSB/PA
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INSTRUCTION SET REFERENCE PADDUSB/P
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INSTRUCTION SET REFERENCE PALIGNR
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INSTRUCTION SET REFERENCE PAND —
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INSTRUCTION SET REFERENCE PANDN —
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Page 145 and 146: INSTRUCTION SET REFERENCE PHADDSW
Page 147 and 148: INSTRUCTION SET REFERENCE PHSUBW/PH
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Page 153 and 154: INSTRUCTION SET REFERENCE PMADDUBSW
Page 155 and 156: INSTRUCTION SET REFERENCE VPMADDWD
Page 157 and 158: INSTRUCTION SET REFERENCE VEX.128 e
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Page 171 and 172: INSTRUCTION SET REFERENCE VPMINUD (
Page 173 and 174: INSTRUCTION SET REFERENCE PMOVMSKB
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Page 179 and 180: INSTRUCTION SET REFERENCE PMOVZX
Page 181 and 182: INSTRUCTION SET REFERENCE Packed_Ze
Page 183 and 184: INSTRUCTION SET REFERENCE Other Exc
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Page 189 and 190: INSTRUCTION SET REFERENCE PMULHUW
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Page 195 and 196: INSTRUCTION SET REFERENCE PMULLW/PM
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Page 201 and 202: INSTRUCTION SET REFERENCE POR — B
Page 203 and 204: INSTRUCTION SET REFERENCE PSADBW
Page 205 and 206: INSTRUCTION SET REFERENCE PSHUFB
Page 207 and 208: INSTRUCTION SET REFERENCE PSHUFD
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Page 213 and 214: INSTRUCTION SET REFERENCE PSIGNB/PS
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Page 217 and 218: INSTRUCTION SET REFERENCE PSLLDQ
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INSTRUCTION SET REFERENCE COUNT 31
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INSTRUCTION SET REFERENCE PSRLDQ
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INSTRUCTION SET REFERENCE PSRLW/PSR
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INSTRUCTION SET REFERENCE FI; DEST[
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INSTRUCTION SET REFERENCE VPSRLQ (x
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE DEST[175:
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INSTRUCTION SET REFERENCE PSUBSB/PS
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INSTRUCTION SET REFERENCE PSUBUSB/P
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INSTRUCTION SET REFERENCE PUNPCKHBW
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INSTRUCTION SET REFERENCE VPUNPCKHW
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INSTRUCTION SET REFERENCE Instructi
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INSTRUCTION SET REFERENCE INTERLEAV
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INSTRUCTION SET REFERENCE VPUNPCKLD
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INSTRUCTION SET REFERENCE SIMD Floa
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INSTRUCTION SET REFERENCE VBROADCAS
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE VPBLENDD
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INSTRUCTION SET REFERENCE VPBROADCA
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INSTRUCTION SET REFERENCE VPERMPD
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INSTRUCTION SET REFERENCE VPERMQ
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INSTRUCTION SET REFERENCE VINSERTI1
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INSTRUCTION SET REFERENCE The secon
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INSTRUCTION SET REFERENCE VPSLLVD/V
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE VPSRAVD (
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INSTRUCTION SET REFERENCE VPSRLVD (
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE This page
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INSTRUCTION SET REFERENCE - FMA VFM
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INSTRUCTION SET REFERENCE - FMA For
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INSTRUCTION SET REFERENCE - FMA sou
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INSTRUCTION SET REFERENCE - FMA Int
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA } I
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INSTRUCTION SET REFERENCE - FMA ope
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INSTRUCTION SET REFERENCE - FMA VFN
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA Thi
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INSTRUCTION SET REFERENCE - VEX-ENC
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INTEL® TRANSACTIONAL SYNCHRONIZATI
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ADDITIONAL NEW INSTRUCTIONS -------
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ADDITIONAL NEW INSTRUCTIONS • If
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ADDITIONAL NEW INSTRUCTIONS ADCX
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ADDITIONAL NEW INSTRUCTIONS ADOX
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ADDITIONAL NEW INSTRUCTIONS Compati
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ADDITIONAL NEW INSTRUCTIONS Flags A
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ADDITIONAL NEW INSTRUCTIONS STAC—
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OPCODE MAP D The reg field of the M
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OPCODE MAP • A ModR/M byte is req
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OPCODE MAP A.2.5 Superscripts Utili
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OPCODE MAP Table A-2. One-byte Opco
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OPCODE MAP 0 1 2 3 4 5 6 7 Table A-
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OPCODE MAP 8 9 A B C D E F Table A-
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OPCODE MAP 0 Table A-4. Three-byte
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OPCODE MAP 0 66 1 66 2 66 3 4 66 5
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OPCODE MAP A.4 OPCODE EXTENSIONS FO
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OPCODE MAP Opcode Group Mod 7,6 pfx
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OPCODE MAP Table A-8 shows the map
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OPCODE MAP Table A-20 shows the opc
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OPCODE MAP This page was intentiona
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INSTRUCTION SUMMARY VEX.256 Encodin
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INSTRUCTION SUMMARY Note 3: It is e
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INSTRUCTION SUMMARY Table B-2. Prom
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INSTRUCTION SUMMARY Table B-3. VEX-
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INSTRUCTION SUMMARY Opcode Instruct
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SSE extensions flag . . . . . . . .
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SSE extensions CPUID flag . . . . .
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I-6 Ref. # 319433-014
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Intel® Architecture Instruction Set Extensions Programming Reference

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