Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SET REFERENCE
PMULLW/PMULLD — Multiply Packed Integers and Store Low Result
Opcode/
Instruction
Description
Op/
En
64/32
-bit
Mode
CPUID
Feature
Flag
Description
66 0F D5 /r A V/V SSE2 Multiply the packed signed word integers in xmm1 and
xmm2/m128, and store the low 16 bits of the results in xmm1.
PMULLW xmm1, xmm2/m128
66 0F 38 40 /r A V/V SSE4_1 Multiply the packed dword signed integers in xmm1 and
xmm2/m128 and store the low 32 bits of each product in xmm1.
PMULLD xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG D5 /r B V/V AVX Multiply the packed signed word integers in xmm2 and
xmm3/m128, and store the low 16 bits of the results in xmm1.
VPMULLW xmm1, xmm2,
xmm3/m128
VEX.NDS.128.66.0F38.WIG 40 /r B V/V AVX Multiply the packed dword signed integers in xmm2 and
xmm3/m128 and store the low 32 bits of each product in xmm1.
VPMULLD xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F.WIG D5 /r B V/V AVX2 Multiply the packed signed word integers in ymm2 and
ymm3/m256, and store the low 16 bits of the results in ymm1.
VPMULLW ymm1, ymm2,
ymm3/m256
VEX.NDS.256.66.0F38.WIG 40 /r B V/V AVX2 Multiply the packed dword signed integers in ymm2 and
ymm3/m256 and store the low 32 bits of each product in ymm1.
VPMULLD ymm1, ymm2,
ymm3/m256
Instruction Operand Encoding
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
B ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA
Performs a SIMD signed multiply of the packed signed word (dword) integers in the first source operand and the
second source operand and stores the low 16(32) bits of each intermediate 32-bit(64-bit) result in the destination
operand.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (255:128) of the corresponding YMM destination
register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (255:128) of the corresponding YMM register are
zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
5-110 Ref. # 319433-014