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Intel® Architecture Instruction Set Extensions Programming Reference

Intel® Architecture Instruction Set Extensions Programming Reference

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INSTRUCTION SET REFERENCE<br />

PMULLW/PMULLD — Multiply Packed Integers and Store Low Result<br />

Opcode/<br />

<strong>Instruction</strong><br />

Description<br />

Op/<br />

En<br />

64/32<br />

-bit<br />

Mode<br />

CPUID<br />

Feature<br />

Flag<br />

Description<br />

66 0F D5 /r A V/V SSE2 Multiply the packed signed word integers in xmm1 and<br />

xmm2/m128, and store the low 16 bits of the results in xmm1.<br />

PMULLW xmm1, xmm2/m128<br />

66 0F 38 40 /r A V/V SSE4_1 Multiply the packed dword signed integers in xmm1 and<br />

xmm2/m128 and store the low 32 bits of each product in xmm1.<br />

PMULLD xmm1, xmm2/m128<br />

VEX.NDS.128.66.0F.WIG D5 /r B V/V AVX Multiply the packed signed word integers in xmm2 and<br />

xmm3/m128, and store the low 16 bits of the results in xmm1.<br />

VPMULLW xmm1, xmm2,<br />

xmm3/m128<br />

VEX.NDS.128.66.0F38.WIG 40 /r B V/V AVX Multiply the packed dword signed integers in xmm2 and<br />

xmm3/m128 and store the low 32 bits of each product in xmm1.<br />

VPMULLD xmm1, xmm2,<br />

xmm3/m128<br />

VEX.NDS.256.66.0F.WIG D5 /r B V/V AVX2 Multiply the packed signed word integers in ymm2 and<br />

ymm3/m256, and store the low 16 bits of the results in ymm1.<br />

VPMULLW ymm1, ymm2,<br />

ymm3/m256<br />

VEX.NDS.256.66.0F38.WIG 40 /r B V/V AVX2 Multiply the packed dword signed integers in ymm2 and<br />

ymm3/m256 and store the low 32 bits of each product in ymm1.<br />

VPMULLD ymm1, ymm2,<br />

ymm3/m256<br />

<strong>Instruction</strong> Operand Encoding<br />

Op/En Operand 1 Operand 2 Operand 3 Operand 4<br />

A ModRM:reg (r, w) ModRM:r/m (r) NA NA<br />

B ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA<br />

Performs a SIMD signed multiply of the packed signed word (dword) integers in the first source operand and the<br />

second source operand and stores the low 16(32) bits of each intermediate 32-bit(64-bit) result in the destination<br />

operand.<br />

128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source<br />

operand is an XMM register or a 128-bit memory location. Bits (255:128) of the corresponding YMM destination<br />

register remain unchanged.<br />

VEX.128 encoded version: The first source and destination operands are XMM registers. The second source<br />

operand is an XMM register or a 128-bit memory location. Bits (255:128) of the corresponding YMM register are<br />

zeroed.<br />

VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The<br />

first source and destination operands are YMM registers.<br />

5-110 Ref. # 319433-014

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