Intel® Architecture Instruction Set Extensions Programming Reference

1.1 ABOUT THIS DOCUMENT
INTEL® ADVANCED VECTOR EXTENSIONS
CHAPTER 1
INTEL® ADVANCED VECTOR EXTENSIONS
This document describes the software programming interfaces of several vector SIMD and general-purpose instruction
extensions of the Intel® 64 architecture that will be introduced with Intel 64 processors built on 22nm
process technology. The Intel AVX extensions are introduced in the second generation Intel® Core processor
family, and details of Intel AVX are covered in the Intel® 64 and IA-32 Architectures Software Developer’s Manual.
Additionally, details of VCVTPH2PS/VCVTPS2PH, RDRAND, RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE
are also covered there.
The instruction set extensions covered in this document are organized in the following chapters:
• 256-bit vector integer instruction extensions, referred to as Intel® AVX2 (also as AVX2), are described in
Chapter 5.
• FMA instruction extensions are described in Chapter 6.
• VEX-encoded, general-purpose instruction extensions are described in Chapter 7.
• Intel Transactional Synchronization Extensions are described in Chapter 8.
Chapter 1 provides an overview of these new instruction set extensions (with Intel AVX included for base reference).
Chapter 2 describes the common application programming environment. Chapter 3 describes system programming
requirements needed to support 256-bit registers. Chapter 4 describes the architectural extensions
of Intel 64 instruction encoding format that support 256-bit registers, three and four operand syntax, and extensions
for vector-index memory addressing and general-purpose register encoding.
1.2 OVERVIEW
Intel® Advanced Vector Extensions extend beyond the capabilities and programming environment over those of
multiple generations of Streaming SIMD Extensions. Intel AVX addresses the continued need for vector floatingpoint
performance in mainstream scientific and engineering numerical applications, visual processing, recognition,
data-mining/synthesis, gaming, physics, cryptography and other areas of applications. Intel AVX is designed
to facilitate efficient implementation by wide spectrum of software architectures of varying degrees of
thread parallelism, and data vector lengths. Intel AVX offers the following benefits:
• efficient building blocks for applications targeted across all segments of computing platforms.
• significant increase in floating-point performance density with good power efficiency over previous generations
of 128-bit SIMD instruction set extensions,
• scalable performance with multi-core processor capability.
Intel AVX also establishes a foundation for future evolution in both instruction set functionality and vector lengths
by introducing an efficient instruction encoding scheme, three and four operand instruction syntax, supporting
load and store masking, etc.
Intel Advanced Vector Extensions offers comprehensive architectural enhancements and functional enhancements
in arithmetic as well as data processing primitives. Section 1.3 summarizes the architectural enhancement
of AVX. Functional overview of AVX and FMA instructions are summarized in Section 1.5. General-purpose encryption
and AES instructions follow the existing architecture of 128-bit SIMD instruction sets like SSE4 and its
predecessors, Section 1.6 provides a short summary.
1.3 INTEL® ADVANCED VECTOR EXTENSIONS ARCHITECTURE OVERVIEW
Intel AVX has many similarities to the SSE and double-precision floating-point portions of SSE2. However, Intel
AVX introduces the following architectural enhancements:
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