Intel® Architecture Instruction Set Extensions Programming Reference

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$Intel® Math Kernel Library (Intel® MKL) 11.0 Release Notes$

$Intel® Math Kernel Library 11.0 Support for Intel® Xeon Phi ...$

Operation VPSUBUSB (VEX.256 encoded version) DEST[7:0] SaturateToUnsignedByte (SRC1[7:0] - SRC2[7:0]); (* Repeat subtract operation for 2nd through 31st bytes *) DEST[255:148] SaturateToUnsignedByte (SRC1[255:248] - SRC2[255:248]); VPSUBUSB (VEX.128 encoded version) DEST[7:0] SaturateToUnsignedByte (SRC1[7:0] - SRC2[7:0]); (* Repeat subtract operation for 2nd through 14th bytes *) DEST[127:120] SaturateToUnsignedByte (SRC1[127:120] - SRC2[127:120]); DEST[VLMAX:128] 0 PSUBUSB (128-bit Legacy SSE Version) DEST[7:0] SaturateToUnsignedByte (DEST[7:0] - SRC[7:0]); (* Repeat subtract operation for 2nd through 14th bytes *) DEST[127:120] SaturateToUnsignedByte (DEST[127:120] - SRC[127:120]); DEST[VLMAX:128] (Unmodified) VPSUBUSW (VEX.256 encoded version) DEST[15:0] SaturateToUnsignedWord (SRC1[15:0] - SRC2[15:0]); (* Repeat subtract operation for 2nd through 15th words *) DEST[255:240] SaturateToUnsignedWord (SRC1[255:240] - SRC2[255:240]); VPSUBUSW (VEX.128 encoded version) DEST[15:0] SaturateToUnsignedWord (SRC1[15:0] - SRC2[15:0]); (* Repeat subtract operation for 2nd through 7th words *) DEST[127:112] SaturateToUnsignedWord (SRC1[127:112] - SRC2[127:112]); DEST[VLMAX:128] 0 PSUBUSW (128-bit Legacy SSE Version) DEST[15:0] SaturateToUnsignedWord (DEST[15:0] - SRC[15:0]); (* Repeat subtract operation for 2nd through 7th words *) DEST[127:112] SaturateToUnsignedWord (DEST[127:112] - SRC[127:112]); DEST[VLMAX:128] (Unmodified) Intel C/C++ Compiler Intrinsic Equivalent (V)PSUBUSB: __m128i _mm_subs_epu8(__m128i m1, __m128i m2) (V)PSUBUSW: __m128i _mm_subs_epu16(__m128i m1, __m128i m2) VPSUBUSB: __m256i _mm256_subs_epu8(__m256i m1, __m256i m2) VPSUBUSW: __m256i _mm256_subs_epu16(__m256i m1, __m256i m2) SIMD Floating-Point Exceptions None Other Exceptions See Exceptions Type 4 INSTRUCTION SET REFERENCE Ref. # 319433-014 5-159
INSTRUCTION SET REFERENCE PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ — Unpack High Data Opcode/ <strong>Instruction</strong> Op/ En 64/32 -bit Mode CPUID Feature Flag Description 66 0F 68/r A V/V SSE2 Interleave high-order bytes from xmm1 and xmm2/m128 into xmm1. PUNPCKHBW xmm1,xmm2/m128 66 0F 69/r A V/V SSE2 Interleave high-order words from xmm1 and xmm2/m128 into xmm1. PUNPCKHWD xmm1,xmm2/m128 66 0F 6A/r A V/V SSE2 Interleave high-order doublewords from xmm1 and xmm2/m128 into xmm1. PUNPCKHDQ xmm1, xmm2/m128 66 0F 6D/r A V/V SSE2 Interleave high-order quadword from xmm1 and xmm2/m128 into xmm1 register. PUNPCKHQDQ xmm1, xmm2/m128 VEX.NDS.128.66.0F.WIG 68 /r B V/V AVX Interleave high-order bytes from xmm2 and xmm3/m128 into xmm1. VPUNPCKHBW xmm1,xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG 69 /r B V/V AVX Interleave high-order words from xmm2 and xmm3/m128 into xmm1. VPUNPCKHWD xmm1,xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG 6A /r B V/V AVX Interleave high-order doublewords from xmm2 and xmm3/m128 into xmm1. VPUNPCKHDQ xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F.WIG 6D /r B V/V AVX Interleave high-order quadword from xmm2 and xmm3/m128 into xmm1 register. VPUNPCKHQDQ xmm1, xmm2, xmm3/m128 VEX.NDS.256.66.0F.WIG 68 /r B V/V AVX2 Interleave high-order bytes from ymm2 and ymm3/m256 into ymm1 register. VPUNPCKHBW ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG 69 /r B V/V AVX2 Interleave high-order words from ymm2 and ymm3/m256 into ymm1 register. VPUNPCKHWD ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG 6A /r B V/V AVX2 Interleave high-order doublewords from ymm2 and ymm3/m256 into ymm1 register. VPUNPCKHDQ ymm1, ymm2, ymm3/m256 VEX.NDS.256.66.0F.WIG 6D /r B V/V AVX2 Interleave high-order quadword from ymm2 and ymm3/m256 into ymm1 register. VPUNPCKHQDQ ymm1, ymm2, ymm3/m256 5-160 Ref. # 319433-014
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Intel® Architecture Instruction Se
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CONTENTS CHAPTER 1 INTEL® ADVANCED
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PANDN — Logical AND NOT . . . . .
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BZHI — Zero High Bits Starting wi
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TABLES 2-1 Rounding behavior of Zer
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FIGURES Figure 2-1. General Procedu
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INTEL® ADVANCED VECTOR EXTENSIONS
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APPLICATION PROGRAMMING MODEL Prior
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APPLICATION PROGRAMMING MODEL } and
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APPLICATION PROGRAMMING MODEL Scala
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APPLICATION PROGRAMMING MODEL x (mu
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APPLICATION PROGRAMMING MODEL Instr
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APPLICATION PROGRAMMING MODEL Table
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APPLICATION PROGRAMMING MODEL Excep
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APPLICATION PROGRAMMING MODEL 2.7.2
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APPLICATION PROGRAMMING MODEL EAX 3
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APPLICATION PROGRAMMING MODEL • T
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APPLICATION PROGRAMMING MODEL How B
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APPLICATION PROGRAMMING MODEL
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APPLICATION PROGRAMMING MODEL EAX[1
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APPLICATION PROGRAMMING MODEL EBX
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SYSTEM PROGRAMMING MODEL • Verify
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SYSTEM PROGRAMMING MODEL The proces
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SYSTEM PROGRAMMING MODEL 3.3 RESET
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INSTRUCTION FORMAT 4.1.1 VEX and th
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INSTRUCTION FORMAT (Bit Position) 7
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INSTRUCTION FORMAT The VEX.vvvv fie
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INSTRUCTION FORMAT 4.1.8 The Third
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INSTRUCTION FORMAT NOTES: 1. If Mod
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INSTRUCTION SET REFERENCE (V)ADDSD
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INSTRUCTION SET REFERENCE register
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INSTRUCTION SET REFERENCE MPSADBW
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INSTRUCTION SET REFERENCE SRC2_BYTE
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INSTRUCTION SET REFERENCE VMPSADBW
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INSTRUCTION SET REFERENCE DEST[79:6
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INSTRUCTION SET REFERENCE Operation
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INSTRUCTION SET REFERENCE PACKSSWB/
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INSTRUCTION SET REFERENCE PACKUSDW
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INSTRUCTION SET REFERENCE TMP[239:2
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INSTRUCTION SET REFERENCE DEST[119:
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INSTRUCTION SET REFERENCE PADDB/PAD
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INSTRUCTION SET REFERENCE PADDQ (Le
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INSTRUCTION SET REFERENCE PADDSB/PA
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INSTRUCTION SET REFERENCE PADDUSB/P
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INSTRUCTION SET REFERENCE PALIGNR
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INSTRUCTION SET REFERENCE PAND —
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INSTRUCTION SET REFERENCE PANDN —
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INSTRUCTION SET REFERENCE PAVGB/PAV
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INSTRUCTION SET REFERENCE PBLENDVB
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INSTRUCTION SET REFERENCE IF (MASK[
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INSTRUCTION SET REFERENCE PBLENDW
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INSTRUCTION SET REFERENCE ELSE DEST
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE PCMPEQQ (
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE PHADDSW
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INSTRUCTION SET REFERENCE PHSUBW/PH
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INSTRUCTION SET REFERENCE PMADDUBSW
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INSTRUCTION SET REFERENCE VPMADDWD
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INSTRUCTION SET REFERENCE VEX.128 e
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INSTRUCTION SET REFERENCE VPMINUD (
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INSTRUCTION SET REFERENCE PMOVMSKB
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INSTRUCTION SET REFERENCE Opcode/ I
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INSTRUCTION SET REFERENCE VPMOVSXWQ
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INSTRUCTION SET REFERENCE PMOVZX
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INSTRUCTION SET REFERENCE Packed_Ze
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE temp13[31
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INSTRUCTION SET REFERENCE PMULHUW
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE This page
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INSTRUCTION SET REFERENCE - FMA VFM
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INSTRUCTION SET REFERENCE - FMA For
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INSTRUCTION SET REFERENCE - FMA sou
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INSTRUCTION SET REFERENCE - FMA Int
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA } I
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INSTRUCTION SET REFERENCE - FMA ope
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INSTRUCTION SET REFERENCE - FMA VFN
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA Thi
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INSTRUCTION SET REFERENCE - VEX-ENC
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INTEL® TRANSACTIONAL SYNCHRONIZATI
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ADDITIONAL NEW INSTRUCTIONS -------
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ADDITIONAL NEW INSTRUCTIONS • If
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ADDITIONAL NEW INSTRUCTIONS ADCX
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ADDITIONAL NEW INSTRUCTIONS ADOX
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ADDITIONAL NEW INSTRUCTIONS Compati
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ADDITIONAL NEW INSTRUCTIONS Flags A
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ADDITIONAL NEW INSTRUCTIONS STAC—
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OPCODE MAP D The reg field of the M
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OPCODE MAP • A ModR/M byte is req
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OPCODE MAP A.2.5 Superscripts Utili
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OPCODE MAP Table A-2. One-byte Opco
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OPCODE MAP 0 1 2 3 4 5 6 7 Table A-
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OPCODE MAP 8 9 A B C D E F Table A-
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OPCODE MAP 0 Table A-4. Three-byte
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OPCODE MAP 0 66 1 66 2 66 3 4 66 5
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OPCODE MAP A.4 OPCODE EXTENSIONS FO
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OPCODE MAP Opcode Group Mod 7,6 pfx
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OPCODE MAP Table A-8 shows the map
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OPCODE MAP Table A-20 shows the opc
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OPCODE MAP This page was intentiona
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INSTRUCTION SUMMARY VEX.256 Encodin
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INSTRUCTION SUMMARY Note 3: It is e
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INSTRUCTION SUMMARY Table B-2. Prom
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INSTRUCTION SUMMARY Table B-3. VEX-
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INSTRUCTION SUMMARY Opcode Instruct
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SSE extensions flag . . . . . . . .
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SSE extensions CPUID flag . . . . .
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I-6 Ref. # 319433-014
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Intel® Architecture Instruction Set Extensions Programming Reference

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