Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SET REFERENCE
PSHUFD — Shuffle Packed Doublewords
Opcode/
Instruction
Description
Op/
En
64/32
-bit
Mode
CPUID
Feature
Flag
Description
66 0F 70 /r ib A V/V SSE2 Shuffle the doublewords in xmm2/m128 based on the encoding
in imm8 and store the result in xmm1.
PSHUFD xmm1, xmm2/m128, imm8
VEX.128.66.0F.WIG 70 /r ib A V/V AVX Shuffle the doublewords in xmm2/m128 based on the encoding
in imm8 and store the result in xmm1.
VPSHUFD xmm1, xmm2/m128,
imm8
VEX.256.66.0F.WIG 70 /r ib A V/V AVX2 Shuffle the doublewords in ymm2/m256 based on the encoding
in imm8 and store the result in ymm1.
VPSHUFD ymm1, ymm2/m256,
imm8
Instruction Operand Encoding
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (w) ModRM:r/m (r) NA NA
Copies doublewords from the source operand and inserts them in the destination operand at the locations selected
with the immediate control operand. Figure 5-4 shows the operation of the 256-bit VPSHUFD instruction and the
encoding of the order operand. Each 2-bit field in the order operand selects the contents of one doubleword location
within a 128-bit lane and copy to the target element in the destination operand. For example, bits 0 and 1 of
the order operand targets the first doubleword element in the low and high 128-bit lane of the destination operand
for 256-bit VPSHUFD. The encoded value of bits 1:0 of the order operand (see the field encoding in Figure 5-4)
determines which doubleword element (from the respective 128-bit lane) of the source operand will be copied to
doubleword 0 of the destination operand.
For 128-bit operation, only the low 128-bit lane are operative. The source operand can be an XMM register or a
128-bit memory location. The destination operand is an XMM register. The order operand is an 8-bit immediate.
Note that this instruction permits a doubleword in the source operand to be copied to more than one doubleword
location in the destination operand.
SRC
X7 X6 X5 X4
DEST Y7 Y6 Y5 Y4
Encoding
of Fields in
ORDER
Operand
00B - X4
01B - X5
10B - X6
11B - X7
ORDER
7 6 5 4 3 2 1 0
X3 X2 X1 X0
Y3 Y2 Y1 Y0
Encoding
of Fields in
ORDER
Operand
Figure 5-4. 256-bit VPSHUFD Instruction Operation
00B - X0
01B - X1
10B - X2
11B - X3
5-122 Ref. # 319433-014