Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SET REFERENCE
PALIGNR — Byte Align
Opcode/
Instruction
Description
Op/
En
64/32
-bit
Mode
CPUID
Feature
Flag
Description
66 0F 3A 0F /r ib A V/V SSSE3 Concatenate destination and source operands, extract byte
PALIGNR xmm1, xmm2/m128,
imm8
Instruction Operand Encoding
aligned result shifted to the right by constant value in imm8 and
result is stored in xmm1.
VEX.NDS.128.66.0F3A.WIG 0F /r ib B V/V AVX Concatenate xmm2 and xmm3/m128 into a 32-byte intermedi-
VPALIGNR xmm1, xmm2,
xmm3/m128, imm8
ate result, extract byte aligned result shifted to the right by constant
value in imm8 and result is stored in xmm1.
VEX.NDS.256.66.0F3A.WIG 0F /r ib B V/V AVX2 Concatenate pairs of 16 bytes in ymm2 and ymm3/m256 into
VPALIGNR ymm1, ymm2,
ymm3/m256, imm8
32-byte intermediate result, extract byte-aligned, 16-byte result
shifted to the right by constant values in imm8 from each intermediate
result, and two 16-byte results are stored in ymm1
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
B ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA
(V)PALIGNR concatenates two blocks of 16-byte data from the first source operand and the second source operand
into an intermediate 32-byte composite, shifts the composite at byte granularity to the right by a constant immediate,
and extracts the right aligned 16-byte result into the destination. The immediate value is considered
unsigned. Immediate shift counts larger than 32 for 128-bit operands produces a zero result.
Legacy SSE instructions: In 64-bit mode use the REX prefix to access additional registers.
128-bit Legacy SSE version: Bits (255:128) of the corresponding YMM destination register remain unchanged.
VEX.256 encoded version: The first source operand is a YMM register and contains two 16-byte blocks. The second
source operand is a YMM register or a 256-bit memory location containing two 16-byte block. The destination
operand is a YMM register and contain two 16-byte results. The imm8[7:0] is the common shift count used for the
two lower 16-byte block sources and the two upper 16-byte block sources. The low 16-byte block of the two source
operands produce the low 16-byte result of the destination operand, the high 16-byte block of the two source operands
produce the high 16-byte result of the destination operand.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (255:128) of the
corresponding YMM register destination are zeroed.
Concatenation is done with 128-bit data in the first and second source operand for both 128-bit and 256-bit
instructions. The high 128-bits of the intermediate composite 256-bit result came from the 128-bit data from the
first source operand; the low 128-bits of the intermediate result came from the 128-bit data of the second source
operand.
5-34 Ref. # 319433-014