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Intel® Architecture Instruction Set Extensions Programming Reference

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APPLICATION PROGRAMMING MODEL<br />

2.7.10 Exception Type 12 (VEX-only, VSIB mem arg, no AC, no floating-point exceptions)<br />

Exception<br />

Real<br />

Virtual 80x86<br />

Table 2-19. Type 12 Class Exception Conditions<br />

Protected and<br />

Compatibility<br />

64-bit<br />

Cause of Exception<br />

Invalid Opcode, #UD X X VEX prefix<br />

X X VEX prefix:<br />

If XFEATURE_ENABLED_MASK[2:1] != ‘11b’.<br />

If CR4.OSXSAVE[bit 18]=0.<br />

X X X X If preceded by a LOCK prefix (F0H)<br />

X X If any REX, F2, F3, or 66 prefixes precede a VEX prefix<br />

X X X NA If address size attribute is 16 bit<br />

X X X X If ModR/M.mod = ‘11b’<br />

X X X X If ModR/M.rm != ‘100b’<br />

X X X X If any corresponding CPUID feature flag is ‘0’<br />

X X X X If any vector register is used more than once between the destination register,<br />

mask register and the index register in VSIB addressing.<br />

Device Not Available,<br />

#NM<br />

X X X X If CR0.TS[bit 3]=1<br />

Stack, SS(0) X For an illegal address in the SS segment<br />

X If a memory address referencing the SS segment is in a non-canonical form<br />

General Protection,<br />

X For an illegal memory operand effective address in the CS, DS, ES, FS or GS seg-<br />

#GP(0)<br />

ments.<br />

X If the memory address is in a non-canonical form.<br />

X X If any part of the operand lies outside the effective address space from 0 to<br />

FFFFH<br />

Page Fault #PF (faultcode)<br />

X X X For a page fault<br />

Ref. # 319433-014 2-23

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