Intel® Architecture Instruction Set Extensions Programming Reference

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$Intel® Math Kernel Library (Intel® MKL) 11.0 Release Notes$

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VPMASKMOV — Conditional SIMD Integer Packed Loads and Stores Opcode/ Instruction Description Op/ En 64/32 -bit Mode CPUID Feature Flag Description Instruction Operand Encoding INSTRUCTION SET REFERENCE VEX.NDS.128.66.0F38.W0 8C /r A V/V AVX2 Conditionally load dword values from m128 using mask in xmm2 and store in xmm1. VPMASKMOVD xmm1, xmm2, m128 VEX.NDS.256.66.0F38.W0 8C /r A V/V AVX2 Conditionally load dword values from m256 using mask in ymm2 and store in ymm1. VPMASKMOVD ymm1, ymm2, m256 VEX.NDS.128.66.0F38.W1 8C /r A V/V AVX2 Conditionally load qword values from m128 using mask in xmm2 and store in xmm1. VPMASKMOVQ xmm1, xmm2, m128 VEX.NDS.256.66.0F38.W1 8C /r A V/V AVX2 Conditionally load qword values from m256 using mask in ymm2 and store in ymm1. VPMASKMOVQ ymm1, ymm2, m256 VEX.NDS.128.66.0F38.W0 8E /r B V/V AVX2 Conditionally store dword values from xmm2 using mask in xmm1. VPMASKMOVD m128, xmm1, xmm2 VEX.NDS.256.66.0F38.W0 8E /r B V/V AVX2 Conditionally store dword values from ymm2 using mask in ymm1. VPMASKMOVD m256, ymm1, ymm2 VEX.NDS.128.66.0F38.W1 8E /r B V/V AVX2 Conditionally store qword values from xmm2 using mask in xmm1. VPMASKMOVQ m128, xmm1, xmm2 VEX.NDS.256.66.0F38.W1 8E /r B V/V AVX2 Conditionally store qword values from ymm2 using mask in ymm1. VPMASKMOVQ m256, ymm1, ymm2 Op/En Operand 1 Operand 2 Operand 3 Operand 4 A ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA B ModRM:r/m (w) VEX.vvvv ModRM:reg (r) NA Conditionally moves packed data elements from the second source operand into the corresponding data element of the destination operand, depending on the mask bits associated with each data element. The mask bits are specified in the first source operand. The mask bit for each data element is the most significant bit of that element in the first source operand. If a mask is 1, the corresponding data element is copied from the second source operand to the destination operand. If the mask is 0, the corresponding data element is set to zero in the load form of these instructions, and unmodified in the store form. Ref. # 319433-014 5-193
INSTRUCTION SET REFERENCE The second source operand is a memory address for the load form of these instructions. The destination operand is a memory address for the store form of these instructions. The other operands are either XMM registers (for VEX.128 version) or YMM registers (for VEX.256 version). Faults occur only due to mask-bit required memory accesses that caused the faults. Faults will not occur due to referencing any memory location if the corresponding mask bit for that memory location is 0. For example, no faults will be detected if the mask bits are all zero. Unlike previous MASKMOV instructions (MASKMOVQ and MASKMOVDQU), a nontemporal hint is not applied to these instructions. Instruction behavior on alignment check reporting with mask bits of less than all 1s are the same as with mask bits of all 1s. VMASKMOV should not be used to access memory mapped I/O as the ordering of the individual loads or stores it does is implementation specific. In cases where mask bits indicate data should not be loaded or stored paging A and D bits will be set in an implementation dependent way. However, A and D bits are always set for pages where data is actually loaded/stored. Note: for load forms, the first source (the mask) is encoded in VEX.vvvv; the second source is encoded in rm_field, and the destination register is encoded in reg_field. Note: for store forms, the first source (the mask) is encoded in VEX.vvvv; the second source register is encoded in reg_field, and the destination memory location is encoded in rm_field. Operation VPMASKMOVD - 256-bit load DEST[31:0] IF (SRC1[31]) Load_32(mem) ELSE 0 DEST[63:32] IF (SRC1[63]) Load_32(mem + 4) ELSE 0 DEST[95:64] IF (SRC1[95]) Load_32(mem + 8) ELSE 0 DEST[127:96] IF (SRC1[127]) Load_32(mem + 12) ELSE 0 DEST[159:128] IF (SRC1[159]) Load_32(mem + 16) ELSE 0 DEST[191:160] IF (SRC1[191]) Load_32(mem + 20) ELSE 0 DEST[223:192] IF (SRC1[223]) Load_32(mem + 24) ELSE 0 DEST[255:224] IF (SRC1[255]) Load_32(mem + 28) ELSE 0 VPMASKMOVD -128-bit load DEST[31:0] IF (SRC1[31]) Load_32(mem) ELSE 0 DEST[63:32] IF (SRC1[63]) Load_32(mem + 4) ELSE 0 DEST[95:64] IF (SRC1[95]) Load_32(mem + 8) ELSE 0 DEST[127:97] IF (SRC1[127]) Load_32(mem + 12) ELSE 0 DEST[VLMAX:128] 0 VPMASKMOVQ - 256-bit load DEST[63:0] IF (SRC1[63]) Load_64(mem) ELSE 0 DEST[127:64] IF (SRC1[127]) Load_64(mem + 8) ELSE 0 DEST[195:128] IF (SRC1[191]) Load_64(mem + 16) ELSE 0 DEST[255:196] IF (SRC1[255]) Load_64(mem + 24) ELSE 0 VPMASKMOVQ - 128-bit load DEST[63:0] IF (SRC1[63]) Load_64(mem) ELSE 0 DEST[127:64] IF (SRC1[127]) Load_64(mem + 16) ELSE 0 DEST[VLMAX:128] 0 5-194 Ref. # 319433-014
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Intel® Architecture Instruction Se
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CONTENTS CHAPTER 1 INTEL® ADVANCED
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PANDN — Logical AND NOT . . . . .
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BZHI — Zero High Bits Starting wi
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TABLES 2-1 Rounding behavior of Zer
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FIGURES Figure 2-1. General Procedu
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INTEL® ADVANCED VECTOR EXTENSIONS
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APPLICATION PROGRAMMING MODEL Prior
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APPLICATION PROGRAMMING MODEL } and
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APPLICATION PROGRAMMING MODEL Scala
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APPLICATION PROGRAMMING MODEL x (mu
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APPLICATION PROGRAMMING MODEL Instr
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APPLICATION PROGRAMMING MODEL Table
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APPLICATION PROGRAMMING MODEL Excep
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APPLICATION PROGRAMMING MODEL 2.7.2
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APPLICATION PROGRAMMING MODEL EAX 3
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APPLICATION PROGRAMMING MODEL • T
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APPLICATION PROGRAMMING MODEL How B
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APPLICATION PROGRAMMING MODEL
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APPLICATION PROGRAMMING MODEL EAX[1
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APPLICATION PROGRAMMING MODEL EBX
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SYSTEM PROGRAMMING MODEL • Verify
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SYSTEM PROGRAMMING MODEL The proces
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SYSTEM PROGRAMMING MODEL 3.3 RESET
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INSTRUCTION FORMAT 4.1.1 VEX and th
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INSTRUCTION FORMAT (Bit Position) 7
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INSTRUCTION FORMAT The VEX.vvvv fie
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INSTRUCTION FORMAT 4.1.8 The Third
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INSTRUCTION FORMAT NOTES: 1. If Mod
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INSTRUCTION SET REFERENCE (V)ADDSD
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INSTRUCTION SET REFERENCE register
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INSTRUCTION SET REFERENCE MPSADBW
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INSTRUCTION SET REFERENCE SRC2_BYTE
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INSTRUCTION SET REFERENCE VMPSADBW
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INSTRUCTION SET REFERENCE DEST[79:6
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INSTRUCTION SET REFERENCE Operation
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INSTRUCTION SET REFERENCE PACKSSWB/
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INSTRUCTION SET REFERENCE PACKUSDW
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INSTRUCTION SET REFERENCE TMP[239:2
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INSTRUCTION SET REFERENCE DEST[119:
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INSTRUCTION SET REFERENCE PADDB/PAD
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INSTRUCTION SET REFERENCE PADDQ (Le
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INSTRUCTION SET REFERENCE PADDSB/PA
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INSTRUCTION SET REFERENCE PADDUSB/P
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INSTRUCTION SET REFERENCE PALIGNR
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INSTRUCTION SET REFERENCE PAND —
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INSTRUCTION SET REFERENCE PANDN —
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INSTRUCTION SET REFERENCE PAVGB/PAV
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INSTRUCTION SET REFERENCE PBLENDVB
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INSTRUCTION SET REFERENCE IF (MASK[
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INSTRUCTION SET REFERENCE PBLENDW
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INSTRUCTION SET REFERENCE ELSE DEST
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE PCMPEQQ (
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE PHADDSW
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INSTRUCTION SET REFERENCE PHSUBW/PH
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INSTRUCTION SET REFERENCE PMADDUBSW
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INSTRUCTION SET REFERENCE VPMADDWD
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INSTRUCTION SET REFERENCE VEX.128 e
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INSTRUCTION SET REFERENCE VPMINUD (
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INSTRUCTION SET REFERENCE PMOVMSKB
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INSTRUCTION SET REFERENCE Opcode/ I
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INSTRUCTION SET REFERENCE VPMOVSXWQ
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INSTRUCTION SET REFERENCE PMOVZX
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INSTRUCTION SET REFERENCE Packed_Ze
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE temp13[31
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INSTRUCTION SET REFERENCE PMULHUW
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE PMULLW/PM
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INSTRUCTION SET REFERENCE Temp10[31
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INSTRUCTION SET REFERENCE PMULUDQ
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INSTRUCTION SET REFERENCE POR — B
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INSTRUCTION SET REFERENCE PSADBW
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INSTRUCTION SET REFERENCE PSHUFB
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INSTRUCTION SET REFERENCE PSHUFD
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INSTRUCTION SET REFERENCE PSHUFHW
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INSTRUCTION SET REFERENCE PSHUFLW
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INSTRUCTION SET REFERENCE PSIGNB/PS
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INSTRUCTION SET REFERENCE DEST[255.
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INSTRUCTION SET REFERENCE PSLLDQ
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INSTRUCTION SET REFERENCE PSLLW/PSL
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INSTRUCTION SET REFERENCE PSLLD (xm
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INSTRUCTION SET REFERENCE PSRAW/PSR
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Page 229 and 230: INSTRUCTION SET REFERENCE PSRLDQ
Page 231 and 232: INSTRUCTION SET REFERENCE PSRLW/PSR
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Page 235 and 236: INSTRUCTION SET REFERENCE VPSRLQ (x
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Page 241 and 242: INSTRUCTION SET REFERENCE PSUBSB/PS
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Page 249 and 250: INSTRUCTION SET REFERENCE VPUNPCKHW
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Page 265 and 266: INSTRUCTION SET REFERENCE VPBLENDD
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Page 271 and 272: INSTRUCTION SET REFERENCE VPERMPD
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Page 289 and 290: INSTRUCTION SET REFERENCE VGATHERDP
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Page 301 and 302: INSTRUCTION SET REFERENCE VPGATHERD
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Page 305 and 306: INSTRUCTION SET REFERENCE This page
Page 307 and 308: INSTRUCTION SET REFERENCE - FMA VFM
Page 309 and 310: INSTRUCTION SET REFERENCE - FMA For
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INSTRUCTION SET REFERENCE - FMA VFM
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INSTRUCTION SET REFERENCE - FMA } I
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INSTRUCTION SET REFERENCE - FMA ope
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INSTRUCTION SET REFERENCE - FMA VFN
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INSTRUCTION SET REFERENCE - FMA Int
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA Int
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA Thi
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INSTRUCTION SET REFERENCE - VEX-ENC
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INTEL® TRANSACTIONAL SYNCHRONIZATI
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ADDITIONAL NEW INSTRUCTIONS -------
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ADDITIONAL NEW INSTRUCTIONS • If
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ADDITIONAL NEW INSTRUCTIONS ADCX
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ADDITIONAL NEW INSTRUCTIONS ADOX
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ADDITIONAL NEW INSTRUCTIONS Compati
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ADDITIONAL NEW INSTRUCTIONS Flags A
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ADDITIONAL NEW INSTRUCTIONS STAC—
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OPCODE MAP D The reg field of the M
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OPCODE MAP • A ModR/M byte is req
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OPCODE MAP A.2.5 Superscripts Utili
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OPCODE MAP Table A-2. One-byte Opco
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OPCODE MAP 0 1 2 3 4 5 6 7 Table A-
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OPCODE MAP 8 9 A B C D E F Table A-
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OPCODE MAP 0 Table A-4. Three-byte
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OPCODE MAP 0 66 1 66 2 66 3 4 66 5
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OPCODE MAP A.4 OPCODE EXTENSIONS FO
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OPCODE MAP Opcode Group Mod 7,6 pfx
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OPCODE MAP Table A-8 shows the map
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OPCODE MAP Table A-20 shows the opc
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OPCODE MAP This page was intentiona
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INSTRUCTION SUMMARY VEX.256 Encodin
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INSTRUCTION SUMMARY Note 3: It is e
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INSTRUCTION SUMMARY Table B-2. Prom
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INSTRUCTION SUMMARY Table B-3. VEX-
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INSTRUCTION SUMMARY Opcode Instruct
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SSE extensions flag . . . . . . . .
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SSE extensions CPUID flag . . . . .
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I-6 Ref. # 319433-014
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Intel® Architecture Instruction Set Extensions Programming Reference

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