Intel® Architecture Instruction Set Extensions Programming Reference

9.4 INSTRUCTION EXCEPTION SPECIFICATION
ADDITIONAL NEW INSTRUCTIONS
To use this reference of instruction exceptions, look at each instruction for a description of the particular exception
type of interest. The instruction’s corresponding CPUID feature flag can be identified in the fourth column of the
instruction summary table.
Note: #UD on CPUID feature flags=0 is not guaranteed in a virtualized environment if the hardware supports the
feature flag.
Table 9-1 lists exception conditions for ADCX and ADOX.
Exception
9.5 INSTRUCTION FORMAT
Table 9-1. Exception Definition (ADCX and ADOX Instructions)
Real
Virtual 80x86
Protected and
Compatibility
64-bit
Cause of Exception
Invalid Opcode, #UD X X X X If ADX CPUID feature flag is ‘0’.
X X X X If a LOCK prefix is present.
Stack, SS(0) X X X For an illegal address in the SS segment.
X If a memory address referencing the SS segment is in a non-canonical form.
General Protection, #GP(0) X For an illegal memory operand effective address in the CS, DS, ES, FS or GS
segments.
If the DS, ES, FS, or GS register is used to access memory and it contains a
null segment selector.
X If the memory address is in a non-canonical form.
X X If any part of the operand lies outside the effective address space from 0 to
FFFFH.
Page Fault #PF(fault-code) X X X For a page fault.
Alignment Check #AC(0) X X X If alignment checking is enabled and an unaligned memory reference is
made while the current privilege level is 3.
The format used for describing each instruction as in the example below is described in Chapter 3 of the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 2A.
Ref. # 319433-014 9-5