Intel® Architecture Instruction Set Extensions Programming Reference

VEX.256
Encoding
VEX.128
Encoding
Table B-1. Promoted SSE/SSE2/SSE3/SSSE3/SSE4 Instructions in AVX
Group Instruction If No, Reason?
no yes PMAXSD VI
no yes PMAXUD VI
no yes PMAXUW VI
no yes PMINSB VI
no yes PMINSD VI
no yes PMINUD VI
no yes PMINUW VI
no yes PMOVSXxx VI
no yes PMOVZXxx VI
no yes PMULDQ VI
no yes PMULLD VI
yes yes PTEST
yes yes ROUNDPD
yes yes ROUNDPS
no yes ROUNDSD scalar
no yes ROUNDSS scalar
no yes SSE4.2 PCMPGTQ VI
no no SSE4.2 CRC32c integer
no yes PCMPESTRI VI
no yes PCMPESTRM VI
no yes PCMPISTRI VI
no yes PCMPISTRM VI
no no POPCNT POPCNT integer
no yes AESNI AESDEC VI
no yes AESDECLAST VI
no yes AESENC VI
no yes AESECNLAST VI
no yes AESIMC VI
no yes AESKEYGENASSIST VI
no yes CLMUL PCLMULQDQ VI
INSTRUCTION SUMMARY
Description of Column “If No, Reason?”
MMX: Instructions referencing MMX registers do not support VEX.
Scalar: Scalar instructions are not promoted to 256-bit.
integer: Integer instructions are not promoted.
VI: “Vector Integer” instructions are not promoted to 256-bit.
Note 1: MOVLPD/PS and MOVHPD/PS are not promoted to 256-bit. The equivalent functionality are provided by
VINSERTF128 and VEXTRACTF128 instructions as the existing instructions have no natural 256b extension.
Note 2: BLENDVPD and BLENDVPS are superseded by the more flexible VBLENDVPD and VBLENDVPS.
Ref. # 319433-014 B-7