Intel® Architecture Instruction Set Extensions Programming Reference

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$Intel® Math Kernel Library (Intel® MKL) 11.0 Release Notes$

$Intel® Math Kernel Library 11.0 Support for Intel® Xeon Phi ...$

Table A-2. One-byte Opcode Map: (08H — FFH) * OPCODE MAP 8 9 A B C D E F 0 OR PUSH CSi64 Eb, Gb Ev, Gv Gb, Eb Gv, Ev AL, Ib rAX, Iz 2-byte escape (Table A-3) 1 SBB PUSH DSi64 POP DSi64 Eb, Gb Ev, Gv Gb, Eb Gv, Ev AL, Ib rAX, Iz 2 SUB SEG=CS DAS (Prefix) i64 Eb, Gb Ev, Gv Gb, Eb Gv, Ev AL, Ib rAX, Iz 3 CMP SEG=DS AAS (Prefix) i64 Eb, Gb Ev, Gv Gb, Eb Gv, Ev AL, Ib rAX, Iz 4 DECi64 general register / REXo64 Prefixes eAX eCX eDX eBX eSP eBP eSI eDI REX.W REX.WB REX.WX REX.WXB REX.WR REX.WRB REX.WRX REX.WRXB 5 POPd64 into general register rAX/r8 rCX/r9 rDX/r10 rBX/r11 rSP/r12 rBP/r13 rSI/r14 rDI/r15 6 PUSH d64 IMUL PUSH Iz Gv, Ev, Iz d64 IMUL INS/ INS/ OUTS/ OUTS/ Ib Gv, Ev, Ib INSB INSW/ OUTSB OUTSW/ Yb, DX INSD DX, Xb OUTSD Yz, DX DX, Xz 7 Jccf64 , Jb- Short displacement jump on condition S NS P/PE NP/PO L/NGE NL/GE LE/NG NLE/G 8 MOV MOV Eb, Gb Ev, Gv Gb, Eb Gv, Ev Ev, Sw 9 CBW/ CWDE/ CDQE CWD/ CDQ/ CQO CALLF i64 Ap FWAIT/ WAIT PUSHF/D/Q d64 / Fv Ref. # 319433-014 A-9 LEA Gv, M POPF/D/Q d64 / Fv MOV Sw, Ew Grp 1A 1A POP d64 Ev SAHF LAHF A TEST STOS/B STOS/W/D/Q LODS/B LODS/W/D/Q SCAS/B SCAS/W/D/Q AL, Ib rAX, Iz Yb, AL Yv, rAX AL, Xb rAX, Xv AL, Yb rAX, Xv B MOV immediate word or double into word, double, or quad register rAX/r8, Iv rCX/r9, Iv rDX/r10, Iv rBX/r11, Iv rSP/r12, Iv rBP/r13, Iv rSI/r14, Iv rDI/r15 , Iv C ENTER LEAVE d64 RETF RETF INT 3 INT INTO i64 IRET/D/Q Iw, Ib Iw Ib D ESC (Escape to coprocessor instruction set) E CALL f64 JMP IN OUT Jz nearf64 far Jz i64 short Ap f64 AL, DX eAX, DX DX, AL DX, eAX Jb F CLC STC CLI STI CLD STD INC/DEC INC/DEC Grp 4 1A Grp 5 1A NOTES: * All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.
OPCODE MAP 0 1 2 3 4 5 6 7 Table A-3. Two-byte Opcode Map: 00H — 77H (First Byte is 0FH) * pfx 0 1 2 3 4 5 6 7 66 F3 F2 66 F3 F2 66 F3 66 F3 F2 Grp 6 1A Grp 7 1A LAR Gv, Ew vmovups Vps, Wps vmovupd Vpd, Wpd vmovss Vx, Hx, Wss vmovsd Vx, Hx, Wsd MOV Rd, Cd vmovups Wps, Vps vmovupd Wpd,Vpd vmovss Wss, Hx, Vss vmovsd Wsd, Hx, Vsd MOV Rd, Dd vmovlps Vq, Hq, Mq vmovhlps Vq, Hq, Uq vmovlpd Vq, Hq, Mq vmovsldup Vx, Wx vmovddup Vx, Wx MOV Cd, Rd LSL Gv, Ew vmovlps Mq, Vq vmovlpd Mq, Vq MOV Dd, Rd vunpcklps Vx, Hx, Wx vunpcklpd Vx,Hx,Wx SYSCALL o64 CLTS SYSRET o64 vunpckhps Vx, Hx, Wx vunpckhpd Vx,Hx,Wx vmovhps v1 Vdq, Hq, Mq vmovlhps Vdq, Hq, Uq vmovhpd v1 Vdq, Hq, Mq vmovshdup Vx, Wx vmovhps v1 Mq, Vq vmovhpd v1 Mq, Vq WRMSR RDTSC RDMSR RDPMC SYSENTER SYSEXIT GETSEC CMOVcc, (Gv, Ev) - Conditional Move O NO B/C/NAE AE/NB/NC E/Z NE/NZ BE/NA A/NBE vmovmskps Gy, Ups vmovmskpd Gy,Upd punpcklbw Pq, Qd vpunpcklbw Vx, Hx, Wx pshufw Pq, Qq, Ib vpshufd Vx, Wx, Ib vpshufhw Vx, Wx, Ib vpshuflw Vx, Wx, Ib vsqrtps Vps, Wps vsqrtpd Vpd, Wpd vsqrtss Vss, Hss, Wss vsqrtsd Vsd, Hsd, Wsd punpcklwd Pq, Qd vpunpcklwd Vx, Hx, Wx vrsqrtps Vps, Wps vrsqrtss Vss, Hss, Wss punpckldq Pq, Qd vpunpckldq Vx, Hx, Wx vrcpps Vps, Wps vrcpss Vss, Hss, Wss packsswb Pq, Qq vpacksswb Vx, Hx, Wx vandps Vps, Hps, Wps vandpd Vpd, Hpd, Wpd vandnps Vps, Hps, Wps vandnpd Vpd, Hpd, Wpd vorps Vps, Hps, Wps vorpd Vpd, Hpd, Wpd vxorps Vps, Hps, Wps vxorpd Vpd, Hpd, Wpd A-10 Ref. # 319433-014 pcmpgtb Pq, Qq vpcmpgtb Vx, Hx, Wx (Grp 12 1A ) (Grp 13 1A ) (Grp 14 1A ) pcmpeqb Pq, Qq vpcmpeqb Vx, Hx, Wx pcmpgtw Pq, Qq vpcmpgtw Vx, Hx, Wx pcmpeqw Pq, Qq vpcmpeqw Vx, Hx, Wx pcmpgtd Pq, Qq vpcmpgtd Vx, Hx, Wx pcmpeqd Pq, Qq vpcmpeqd Vx, Hx, Wx packuswb Pq, Qq vpackuswb Vx, Hx, Wx emms vzeroupper v vzeroall v
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Intel® Architecture Instruction Se
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CONTENTS CHAPTER 1 INTEL® ADVANCED
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PANDN — Logical AND NOT . . . . .
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BZHI — Zero High Bits Starting wi
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TABLES 2-1 Rounding behavior of Zer
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FIGURES Figure 2-1. General Procedu
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INTEL® ADVANCED VECTOR EXTENSIONS
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APPLICATION PROGRAMMING MODEL Prior
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APPLICATION PROGRAMMING MODEL } and
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APPLICATION PROGRAMMING MODEL Scala
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APPLICATION PROGRAMMING MODEL x (mu
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APPLICATION PROGRAMMING MODEL Instr
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APPLICATION PROGRAMMING MODEL Table
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APPLICATION PROGRAMMING MODEL Excep
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APPLICATION PROGRAMMING MODEL 2.7.2
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APPLICATION PROGRAMMING MODEL EAX 3
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APPLICATION PROGRAMMING MODEL • T
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APPLICATION PROGRAMMING MODEL How B
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APPLICATION PROGRAMMING MODEL
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APPLICATION PROGRAMMING MODEL EAX[1
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APPLICATION PROGRAMMING MODEL EBX
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SYSTEM PROGRAMMING MODEL • Verify
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SYSTEM PROGRAMMING MODEL The proces
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SYSTEM PROGRAMMING MODEL 3.3 RESET
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INSTRUCTION FORMAT 4.1.1 VEX and th
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INSTRUCTION FORMAT (Bit Position) 7
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INSTRUCTION FORMAT The VEX.vvvv fie
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INSTRUCTION FORMAT 4.1.8 The Third
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INSTRUCTION FORMAT NOTES: 1. If Mod
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INSTRUCTION SET REFERENCE (V)ADDSD
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INSTRUCTION SET REFERENCE register
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INSTRUCTION SET REFERENCE MPSADBW
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INSTRUCTION SET REFERENCE SRC2_BYTE
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INSTRUCTION SET REFERENCE VMPSADBW
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INSTRUCTION SET REFERENCE DEST[79:6
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INSTRUCTION SET REFERENCE Operation
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INSTRUCTION SET REFERENCE PACKSSWB/
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INSTRUCTION SET REFERENCE PACKUSDW
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INSTRUCTION SET REFERENCE TMP[239:2
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INSTRUCTION SET REFERENCE DEST[119:
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INSTRUCTION SET REFERENCE PADDB/PAD
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INSTRUCTION SET REFERENCE PADDQ (Le
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INSTRUCTION SET REFERENCE PADDSB/PA
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INSTRUCTION SET REFERENCE PADDUSB/P
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INSTRUCTION SET REFERENCE PALIGNR
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INSTRUCTION SET REFERENCE PAND —
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INSTRUCTION SET REFERENCE PANDN —
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INSTRUCTION SET REFERENCE PAVGB/PAV
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INSTRUCTION SET REFERENCE PBLENDVB
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INSTRUCTION SET REFERENCE IF (MASK[
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INSTRUCTION SET REFERENCE PBLENDW
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INSTRUCTION SET REFERENCE ELSE DEST
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE PCMPEQQ (
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE PHADDSW
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INSTRUCTION SET REFERENCE PHSUBW/PH
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INSTRUCTION SET REFERENCE PMADDUBSW
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INSTRUCTION SET REFERENCE VPMADDWD
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INSTRUCTION SET REFERENCE VEX.128 e
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INSTRUCTION SET REFERENCE VPMINUD (
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INSTRUCTION SET REFERENCE PMOVMSKB
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INSTRUCTION SET REFERENCE Opcode/ I
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INSTRUCTION SET REFERENCE VPMOVSXWQ
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INSTRUCTION SET REFERENCE PMOVZX
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INSTRUCTION SET REFERENCE Packed_Ze
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE temp13[31
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INSTRUCTION SET REFERENCE PMULHUW
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INSTRUCTION SET REFERENCE PMULLW/PM
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INSTRUCTION SET REFERENCE Temp10[31
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INSTRUCTION SET REFERENCE PMULUDQ
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INSTRUCTION SET REFERENCE POR — B
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INSTRUCTION SET REFERENCE PSADBW
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INSTRUCTION SET REFERENCE PSHUFB
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INSTRUCTION SET REFERENCE PSHUFD
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INSTRUCTION SET REFERENCE PSHUFHW
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INSTRUCTION SET REFERENCE PSHUFLW
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INSTRUCTION SET REFERENCE PSIGNB/PS
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INSTRUCTION SET REFERENCE DEST[255.
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INSTRUCTION SET REFERENCE PSLLDQ
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INSTRUCTION SET REFERENCE PSLLW/PSL
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INSTRUCTION SET REFERENCE PSLLD (xm
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INSTRUCTION SET REFERENCE PSRAW/PSR
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INSTRUCTION SET REFERENCE COUNT 31
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INSTRUCTION SET REFERENCE PSRLDQ
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INSTRUCTION SET REFERENCE PSRLW/PSR
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INSTRUCTION SET REFERENCE FI; DEST[
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INSTRUCTION SET REFERENCE VPSRLQ (x
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INSTRUCTION SET REFERENCE PSUBSB/PS
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INSTRUCTION SET REFERENCE PSUBUSB/P
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INSTRUCTION SET REFERENCE PUNPCKHBW
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INSTRUCTION SET REFERENCE VPUNPCKHW
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INSTRUCTION SET REFERENCE Instructi
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INSTRUCTION SET REFERENCE INTERLEAV
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INSTRUCTION SET REFERENCE VPUNPCKLD
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INSTRUCTION SET REFERENCE SIMD Floa
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INSTRUCTION SET REFERENCE VBROADCAS
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INSTRUCTION SET REFERENCE VPBLENDD
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INSTRUCTION SET REFERENCE VPBROADCA
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INSTRUCTION SET REFERENCE VPERMPD
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INSTRUCTION SET REFERENCE VPERMQ
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INSTRUCTION SET REFERENCE VINSERTI1
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INSTRUCTION SET REFERENCE The secon
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INSTRUCTION SET REFERENCE VPSLLVD/V
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE VPSRAVD (
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INSTRUCTION SET REFERENCE VPSRLVD (
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE This page
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INSTRUCTION SET REFERENCE - FMA VFM
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INSTRUCTION SET REFERENCE - FMA For
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INSTRUCTION SET REFERENCE - FMA sou
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INSTRUCTION SET REFERENCE - FMA Int
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA } I
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INSTRUCTION SET REFERENCE - FMA ope
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INSTRUCTION SET REFERENCE - FMA VFN
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA Thi
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INSTRUCTION SET REFERENCE - VEX-ENC
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Page 377 and 378: INSTRUCTION SET REFERENCE - VEX-ENC
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Page 407 and 408: ADDITIONAL NEW INSTRUCTIONS -------
Page 409 and 410: ADDITIONAL NEW INSTRUCTIONS • If
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Page 413 and 414: ADDITIONAL NEW INSTRUCTIONS ADOX
Page 415 and 416: ADDITIONAL NEW INSTRUCTIONS Compati
Page 417 and 418: ADDITIONAL NEW INSTRUCTIONS Flags A
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Page 421 and 422: OPCODE MAP D The reg field of the M
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Page 431 and 432: OPCODE MAP 8 9 A B C D E F Table A-
Page 433 and 434: OPCODE MAP 0 Table A-4. Three-byte
Page 435 and 436: OPCODE MAP 0 66 1 66 2 66 3 4 66 5
Page 437 and 438: OPCODE MAP A.4 OPCODE EXTENSIONS FO
Page 439 and 440: OPCODE MAP Opcode Group Mod 7,6 pfx
Page 441 and 442: OPCODE MAP Table A-8 shows the map
Page 447 and 448: OPCODE MAP Table A-20 shows the opc
Page 449 and 450: OPCODE MAP This page was intentiona
Page 451 and 452: INSTRUCTION SUMMARY VEX.256 Encodin
Page 457 and 458: INSTRUCTION SUMMARY Note 3: It is e
Page 459 and 460: INSTRUCTION SUMMARY Table B-2. Prom
Page 461 and 462: INSTRUCTION SUMMARY Table B-3. VEX-
Page 463 and 464: INSTRUCTION SUMMARY Opcode Instruct
Page 473 and 474: SSE extensions flag . . . . . . . .
Page 475 and 476: SSE extensions CPUID flag . . . . .
Page 477: I-6 Ref. # 319433-014
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Intel® Architecture Instruction Set Extensions Programming Reference

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