Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SET REFERENCE
VGATHERDPD/VGATHERQPD — Gather Packed DP FP Values Using Signed Dword/Qword Indices
Opcode/
Instruction
Description
Op/
En
64/3
2-bit
Mode
CPUID
Feature
Flag
Description
VEX.DDS.128.66.0F38.W1 92 /r A V/V AVX2 Using dword indices specified in vm32x, gather double-preci-
VGATHERDPD xmm1, vm32x, xmm2
sion FP values from memory conditioned on mask specified by
xmm2. Conditionally gathered elements are merged into xmm1.
VEX.DDS.128.66.0F38.W1 93 /r A V/V AVX2 Using qword indices specified in vm64x, gather double-preci-
VGATHERQPD xmm1, vm64x, xmm2
sion FP values from memory conditioned on mask specified by
xmm2. Conditionally gathered elements are merged into xmm1.
VEX.DDS.256.66.0F38.W1 92 /r A V/V AVX2 Using dword indices specified in vm32x, gather double-preci-
VGATHERDPD ymm1, vm32x, ymm2
sion FP values from memory conditioned on mask specified by
ymm2. Conditionally gathered elements are merged into ymm1.
VEX.DDS.256.66.0F38.W1 93 /r A V/V AVX2 Using qword indices specified in vm64y, gather double-preci-
VGATHERQPD ymm1, vm64y, ymm2
sion FP values from memory conditioned on mask specified by
ymm2. Conditionally gathered elements are merged into ymm1.
Instruction Operand Encoding
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r,w) BaseReg (R): VSIB:base,
VectorReg(R): VSIB:index
VEX.vvvv (r, w) NA
The instruction conditionally loads up to 2 or 4 double-precision floating-point values from memory addresses
specified by the memory operand (the second operand) and using qword indices. The memory operand uses the
VSIB form of the SIB byte to specify a general purpose register operand as the common base, a vector register for
an array of indices relative to the base and a constant scale factor.
The mask operand (the third operand) specifies the conditional load operation from each memory address and the
corresponding update of each data element of the destination operand (the first operand). Conditionality is specified
by the most significant bit of each data element of the mask register. If an element’s mask bit is not set, the
corresponding element of the destination register is left unchanged. The width of data element in the destination
register and mask register are identical. The entire mask register will be set to zero by this instruction unless the
instruction causes an exception.
Using dword indices in the lower half of the mask register, the instruction conditionally loads up to 2 or 4 doubleprecision
floating-point values from the VSIB addressing memory operand, and updates the destination register.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask operand are partially updated; those elements that have been gathered are placed into the
destination register and have their mask bits set to zero. If any traps or interrupts are pending from already gathered
elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction
breakpoint is not re-triggered when the instruction is continued.
If the data size and index size are different, part of the destination register and part of the mask register do not
correspond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both
of those registers even if the instruction triggers an exception, and even if the instruction triggers the exception
before gathering any elements.
VEX.128 version: The instruction will gather two double-precision floating-point values. For dword indices, only the
lower two indices in the vector index register are used.
VEX.256 version: The instruction will gather four double-precision floating-point values. For dword indices, only
the lower four indices in the vector index register are used.
5-204 Ref. # 319433-014