Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SET REFERENCE
PSHUFB — Packed Shuffle Bytes
Opcode/
Instruction
Description
Instruction Operand Encoding
PSHUFB performs in-place shuffles of bytes in the first source operand according to the shuffle control mask in the
second source operand. The instruction permutes the data in the first source operand, leaving the shuffle mask
unaffected. If the most significant bit (bit[7]) of each byte of the shuffle control mask is set, then constant zero is
written in the result byte. Each byte in the shuffle control mask forms an index to permute the corresponding byte
in the first source operand. The value of each index is the least significant 4 bits of the shuffle control byte. The first
source and destination operands are XMM registers. The second source is either an XMM register or a 128-bit
memory location.
128-bit Legacy SSE version: The first source and destination operands are the same. Bits (255:128) of the corresponding
YMM destination register remain unchanged.
VEX.128 encoded version: Bits (255:128) of the destination YMM register are zeroed.
VEX.256 encoded version: Bits (255:128) of the destination YMM register stores the 16-byte shuffle result of the
upper 16 bytes of the first source operand, using the upper 16-bytes of the second source operand as control mask.
The value of each index is for the high 128-bit lane is the least significant 4 bits of the respective shuffle control
byte. The index value selects a source data element within each 128-bit lane.
Operation
Op/
En
64/32
-bit
Mode
CPUID
Feature
Flag
Description
66 0F 38 00 /r A V/V SSSE3 Shuffle bytes in xmm1 according to contents of xmm2/m128.
PSHUFB xmm1, xmm2/m128
VEX.NDS.128.66.0F38.WIG 00 /r B V/V AVX Shuffle bytes in xmm2 according to contents of xmm3/m128.
VPSHUFB xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F38.WIG 00 /r B V/V AVX2 Shuffle bytes in ymm2 according to contents of ymm3/m256.
VPSHUFB ymm1, ymm2,
ymm3/m256
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
B ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA
VPSHUFB (VEX.256 encoded version)
for i = 0 to 15 {
if (SRC2[(i * 8)+7] == 1 ) then
DEST[(i*8)+7..(i*8)+0] 0;
else
index[3..0] SRC2[(i*8)+3 .. (i*8)+0];
DEST[(i*8)+7..(i*8)+0] SRC1[(index*8+7)..(index*8+0)];
endif
if (SRC2[128 + (i * 8)+7] == 1 ) then
DEST[128 + (i*8)+7..(i*8)+0] 0;
else
index[3..0] SRC2[128 + (i*8)+3 .. (i*8)+0];
DEST[128 + (i*8)+7..(i*8)+0] SRC1[128 + (index*8+7)..(index*8+0)];
endif
5-120 Ref. # 319433-014