Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SUMMARY
Table B-6. VEX-Encoded and Other General-Purpose Instruction Sets
Opcode Instruction Description
VEX.NDS.LZ.0F38.W0 F2 /r ANDN r32a, r32b, r/m32 Bitwise AND of inverted r32b with r/m32, store result in r32a
VEX.NDS.LZ.0F38.W1 F2 /r ANDN r64a, r64b, r/m64 Bitwise AND of inverted r64b with r/m64, store result in r64a
VEX.NDS.LZ.0F38.W0 F7 /r BEXTR r32a, r/m32, r32b Contiguous bitwise extract from r/m32 using r32b as control;
store result in r32a.
VEX.NDS.LZ.0F38.W1 F7 /r BEXTR r64a, r/m64, r64b Contiguous bitwise extract from r/m64 using r64b as control;
store result in r64a.
VEX.NDD.LZ.0F38.W0 F3 /3 BLSI r32, r/m32 Set all lower bits in r32 to “1” starting from bit 0 to lowest set
bit in r/m32
VEX.NDD.LZ.0F38.W1 F3 /3 BLSI r64, r/m64 Set all lower bits in r64 to “1” starting from bit 0 to lowest set
bit in r/m64
VEX.NDD.LZ.0F38.W0 F3 /2 BLSMSK r32, r/m32 Extract lowest bit from r/m32 and set that bit in r32
VEX.NDD.LZ.0F38.W1 F3 /2 BLSMSK r64, r/m64 Extract lowest bit from r/m64 and set that bit in r64
VEX.NDD.LZ.0F38.W0 F3 /1 BLSR r32, r/m32 Reset lowest set bit of r/m32, keep all other bits of r/m32 and
write result to r32
VEX.NDD.LZ.0F38.W1 F3 /1 BLSR r64, r/m64 Reset lowest set bit of r/m64, keep all other bits of r/m64 and
write result to r64
VEX.NDS.LZ.0F38.W0 F5 /r BZHI r32a, r/m32, r32b Zero bits in r/m32 starting with the position in r32b, write
result to r32a.
VEX.NDS.LZ.0F38.W1 F5 /r BZHI r64a, r/m64, r64b Zero bits in r/m64 starting with the position in r64b, write
result to r64a.
F3 0F BD /r LZCNT r16, r/m16 Count the number of leading zero bits in r/m16, return result in
r16
F3 0F BD /r LZCNT r32, r/m32 Count the number of leading zero bits in r/m32, return result in
r32
REX.W + F3 0F BD /r LZCNT r64, r/m64 Count the number of leading zero bits in r/m64, return result in
r64.
VEX.NDD.LZ.F2.0F38.W0 F6 /r MULX r32a, r32b, r/m32 Unsigned multiply of r/m32 with EDX without affecting arithmetic
flags.
VEX.NDD.LZ.F2.0F38.W1 F6 /r MULX r64a, r64b, r/m64 Unsigned multiply of r/m64 with RDX without affecting arithmetic
flags.
VEX.NDS.LZ.F2.0F38.W0 F5 /r PDEP r32a, r32b, r/m32 Parallel deposit of bits from r32b using mask in r/m32, result is
written to r32a.
VEX.NDS.LZ.F2.0F38.W1 F5 /r PDEP r64a, r64b, r/m64 Parallel deposit of bits from r64b using mask in r/m64, result is
written to r64a
VEX.NDS.LZ.F3.0F38.W0 F5 /r PEXT r32a, r32b, r/m32 Parallel extract of bits from r32b using mask in r/m32, result is
written to r32a.
VEX.NDS.LZ.F3.0F38.W1 F5 /r PEXT r64a, r64b, r/m64 Parallel extract of bits from r64b using mask in r/m64, result is
written to r64a
VEX.LZ.0F3A.W0 F0 /r ib RORX r32, r/m32, imm8 Rotate 32-bit r/m32 right imm8 times without affecting arithmetic
flags.
VEX.LZ.0F3A.W1 F0 /r ib RORX r64, r/m64, imm8 Rotate 64-bit r/m64 right imm8 times without affecting arithmetic
flags.
VEX.NDS.LZ.F3.0F38.W0 F7 /r SARX r32a, r/m32, r32b Shift r/m32 arithmetically right with count specified in r32b.
VEX.NDS.LZ.F3.0F38.W1 F7 /r SARX r64a, r/m64, r64b Shift r/m64 arithmetically right with count specified in r64b.
VEX.NDS.LZ.66.0F38.W0 F7 /r SHLX r32a, r/m32, r32b Shift r/m32 logically left with count specified in r32b.
VEX.NDS.LZ.66.0F38.W1 F7 /r SHLX r64a, r/m64, r64b Shift r/m64 logically left with count specified in r64b.
VEX.NDS.LZ.F2.0F38.W0 F7 /r SHRX r32a, r/m32, r32b Shift r/m32 logically right with count specified in r32b.
VEX.NDS.LZ.F2.0F38.W1 F7 /r SHRX r64a, r/m64, r64b Shift r/m64 logically right with count specified in r64b.
Ref. # 319433-014 B-21