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Intel® Architecture Instruction Set Extensions Programming Reference

Intel® Architecture Instruction Set Extensions Programming Reference

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INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS<br />

Outside IA-32e mode, the processor treats INVPCID as if all mappings are associated with PCID 000H.<br />

Operation<br />

INVPCID_TYPE ← value of register operand; // must be in the range of 0-3<br />

INVPCID_DESC ← value of memory operand;<br />

CASE INVPCID_TYPE OF<br />

0: // individual-address invalidation retaining global translations<br />

OP_PCID ← INVPCID_DESC[11:0];<br />

ADDR ← INVPCID_DESC[127:64];<br />

Invalidate mappings for ADDR tagged with OP_PCID except global translations;<br />

BREAK;<br />

1: // single PCID invalidation retaining globals<br />

OP_PCID ← INVPCID_DESC[11:0];<br />

Invalidate all mappings tagged with OP_PCID except global translations;<br />

BREAK;<br />

2: // all PCID invalidation<br />

Invalidate all mappings tagged with any PCID;<br />

BREAK;<br />

3: // all PCID invalidation retaining global translations<br />

Invalidate all mappings tagged with any PCID except global translations;<br />

BREAK;<br />

ESAC;<br />

Intel C/C++ Compiler Intrinsic Equivalent<br />

INVPCID: void _invpcid(unsigned __int32 type, void * descriptor);<br />

SIMD Floating-Point Exceptions<br />

None<br />

Protected Mode Exceptions<br />

#GP(0) If the current privilege level is not 0.<br />

If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.<br />

If the DS, ES, FS, or GS register contains an unusable segment.<br />

If the source operand is located in an execute-only code segment.<br />

If an invalid type is specified in the register operand, i.e., INVPCID_TYPE > 3.<br />

If bits 63:12 of INVPCID_DESC are not all zero.<br />

If CR4.PCIDE=0, INVPCID_DESC[11:0] is not zero, and INVPCID_TYPE is either 0, or 1.<br />

#PF(fault-code) If a page fault occurs in accessing the memory operand.<br />

#SS(0) If the memory operand effective address is outside the SS segment limit.<br />

If the SS register contains an unusable segment.<br />

#UD If if CPUID.(EAX=07H, ECX=0H):EBX.INVPCID (bit 10) = 0.<br />

If the LOCK prefix is used.<br />

Real-Address Mode Exceptions<br />

#GP(0) If an invalid type is specified in the register operand, i.e INVPCID_TYPE > 3.<br />

If bits 63:12 of INVPCID_DESC are not all zero.<br />

If CR4.PCIDE=0, INVPCID_DESC[11:0] is not zero, and INVPCID_TYPE is either 0, or 1.<br />

#UD If CPUID.(EAX=07H, ECX=0H):EBX.INVPCID (bit 10) = 0.<br />

If the LOCK prefix is used.<br />

7-24 Ref. # 319433-014

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