Intel® Architecture Instruction Set Extensions Programming Reference

The format of the header is as follows (see Table 3-4):
SYSTEM PROGRAMMING MODEL
Table 3-3. Layout of XSAVE Area For Processor Supporting YMM State
Save Areas Offset (Byte) Size (Bytes)
FPU/SSE SaveArea 0 512
Header 512 64
Ext_Save_Area_2 (YMM) CPUID.(EAX=0DH, ECX=2):EBX CPUID.(EAX=0DH, ECX=2):EAX
15:8 7:0
Table 3-4. XSAVE Header Format
The layout of the Ext_Save_Area[YMM] contains 16 of the upper 128-bits of the YMM registers, it is shown in
Table 3-5.
3.2.5 XSAVE/XRSTOR Interaction with YMM State and MXCSR
Byte Offset from
Header
Byte Offset from
XSAVE Area
Reserved (Must be zero) XSTATE_BV 0 512
Reserved Reserved (Must be zero) 16 528
Reserved Reserved 32 544
Reserved Reserved 48 560
Table 3-5. XSAVE Save Area Layout for YMM State (Ext_Save_Area_2)
31 16 15 0
Byte Offset from
YMM_Save_Area
Byte Offset from XSAVE Area
YMM1[255:128] YMM0[255:128] 0 576
YMM3[255:128] YMM2[255:128] 32 608
YMM5[255:128] YMM4[255:128] 64 640
YMM7[255:128] YMM6[255:128] 96 672
YMM9[255:128] YMM8[255:128] 128 704
YMM11[255:128] YMM10[255:128] 160 736
YMM13[255:128] YMM12[255:128] 192 768
YMM15[255:128] YMM14[255:128] 224 800
The processor’s action as a result of executing XRSTOR, on the MXCSR, XMM and YMM registers, are listed in Table
3-6 (Both bit 1 and bit 2 of the XFEATURE_ENABLED_MASK register are presumed to be 1). The XMM registers may
be initialized by the processor (See XRSTOR operation in Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2B). When the MXCSR register is updated from memory, reserved bit checking is enforced. The
saving/restoring of MXCSR is bound to both the SSE state and YMM state. MXCSR save/restore will not be bound to
any future states.
Ref. # 319433-014 3-3