Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SET REFERENCE - VEX-ENCODED GPR INSTRUCTIONS
LZCNT— Count the Number of Leading Zero Bits
Opcode/Instruction Op/
En
Description
Instruction Operand Encoding
Counts the number of leading most significant zero bits in a source operand (second operand) returning the result
into a destination (first operand).
LZCNT differs from BSR. For example, LZCNT will produce the operand size when the input operand is zero. It
should be noted that on processors that do not support LZCNT, the instruction byte encoding is executed as BSR.
In 64-bit mode 64-bit operand size requires REX.W=1.
Operation
temp ← OperandSize - 1
DEST ← 0
WHILE (temp >= 0) AND (Bit(SRC, temp) = 0)
DO
temp ← temp - 1
DEST ← DEST+ 1
OD
IF DEST = OperandSize
CF ← 1
ELSE
CF ← 0
FI
IF DEST = 0
ZF ← 1
ELSE
ZF ← 0
FI
64/32
-bit
Mode
CPUID
Feature
Flag
Description
F3 0F BD /r A V/V LZCNT Count the number of leading zero bits in r/m16, return result in r16.
LZCNT r16, r/m16
F3 0F BD /r A V/V LZCNT Count the number of leading zero bits in r/m32, return result in r32.
LZCNT r32, r/m32
REX.W + F3 0F BD /r A V/N.E. LZCNT Count the number of leading zero bits in r/m64, return result in r64.
LZCNT r64, r/m64
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (w) ModRM:r/m (r) NA NA
Flags Affected
ZF flag is set to 1 in case of zero output (most significant bit of the source is set), and to 0 otherwise, CF flag is set
to 1 if input was zero and cleared otherwise. OF, SF, PF and AF flags are undefined.
7-10 Ref. # 319433-014