Intel® Architecture Instruction Set Extensions Programming Reference

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$Intel® Math Kernel Library (Intel® MKL) 11.0 Release Notes$

$Intel® Math Kernel Library 11.0 Support for Intel® Xeon Phi ...$

VPBLENDD — Blend Packed Dwords Opcode/ <strong>Instruction</strong> Description <strong>Instruction</strong> Operand Encoding INSTRUCTION SET REFERENCE Dword elements from the source operand (second operand) are conditionally written to the destination operand (first operand) depending on bits in the immediate operand (third operand). The immediate bits (bits 7:0) form a mask that determines whether the corresponding word in the destination is copied from the source. If a bit in the mask, corresponding to a word, is “1", then the word is copied, else the word is unchanged. VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The first source and destination operands are XMM registers. Bits (255:128) of the corresponding YMM register are zeroed. VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. Operation Op/ En 64/32 -bit Mode VPBLENDD (VEX.256 encoded version) IF (imm8[0] == 1) THEN DEST[31:0] SRC2[31:0] ELSE DEST[31:0] SRC1[31:0] IF (imm8[1] == 1) THEN DEST[63:32] SRC2[63:32] ELSE DEST[63:32] SRC1[63:32] IF (imm8[2] == 1) THEN DEST[95:64] SRC2[95:64] ELSE DEST[95:64] SRC1[95:64] IF (imm8[3] == 1) THEN DEST[127:96] SRC2[127:96] ELSE DEST[127:96] SRC1[127:96] IF (imm8[4] == 1) THEN DEST[159:128] SRC2[159:128] ELSE DEST[159:128] SRC1[159:128] IF (imm8[5] == 1) THEN DEST[191:160] SRC2[191:160] ELSE DEST[191:160] SRC1[191:160] IF (imm8[6] == 1) THEN DEST[223:192] SRC2[223:192] ELSE DEST[223:192] SRC1[223:192] IF (imm8[7] == 1) THEN DEST[255:224] SRC2[255:224] ELSE DEST[255:224] SRC1[255:224] CPUID Feature Flag Description VEX.NDS.128.66.0F3A.W0 02 /r ib A V/V AVX2 Select dwords from xmm2 and xmm3/m128 from mask specified in imm8 and store the values into xmm1. VPBLENDD xmm1, xmm2, xmm3/m128, imm8 VEX.NDS.256.66.0F3A.W0 02 /r ib A V/V AVX2 Select dwords from ymm2 and ymm3/m256 from mask specified in imm8 and store the values into ymm1. VPBLENDD ymm1, ymm2, ymm3/m256, imm8 Op/En Operand 1 Operand 2 Operand 3 Operand 4 A ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA Ref. # 319433-014 5-179
INSTRUCTION SET REFERENCE VPBLENDD (VEX.128 encoded version) IF (imm8[0] == 1) THEN DEST[31:0] SRC2[31:0] ELSE DEST[31:0] SRC1[31:0] IF (imm8[1] == 1) THEN DEST[63:32] SRC2[63:32] ELSE DEST[63:32] SRC1[63:32] IF (imm8[2] == 1) THEN DEST[95:64] SRC2[95:64] ELSE DEST[95:64] SRC1[95:64] IF (imm8[3] == 1) THEN DEST[127:96] SRC2[127:96] ELSE DEST[127:96] SRC1[127:96] DEST[VLMAX:128] 0 Intel C/C++ Compiler Intrinsic Equivalent VPBLENDD: __m128i _mm_blend_epi32 (__m128i v1, __m128i v2, const int mask) VPBLENDD: __m256i _mm256_blend_epi32 (__m256i v1, __m256i v2, const int mask) SIMD Floating-Point Exceptions None Other Exceptions See Exceptions Type 4; additionally #UD If VEX.W = 1. 5-180 Ref. # 319433-014
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Intel® Architecture Instruction Se
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CONTENTS CHAPTER 1 INTEL® ADVANCED
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PANDN — Logical AND NOT . . . . .
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BZHI — Zero High Bits Starting wi
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TABLES 2-1 Rounding behavior of Zer
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FIGURES Figure 2-1. General Procedu
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INTEL® ADVANCED VECTOR EXTENSIONS
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APPLICATION PROGRAMMING MODEL Prior
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APPLICATION PROGRAMMING MODEL } and
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APPLICATION PROGRAMMING MODEL Scala
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APPLICATION PROGRAMMING MODEL x (mu
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APPLICATION PROGRAMMING MODEL Instr
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APPLICATION PROGRAMMING MODEL Table
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APPLICATION PROGRAMMING MODEL Excep
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APPLICATION PROGRAMMING MODEL 2.7.2
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APPLICATION PROGRAMMING MODEL EAX 3
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APPLICATION PROGRAMMING MODEL • T
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APPLICATION PROGRAMMING MODEL How B
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APPLICATION PROGRAMMING MODEL
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APPLICATION PROGRAMMING MODEL EAX[1
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APPLICATION PROGRAMMING MODEL EBX
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SYSTEM PROGRAMMING MODEL • Verify
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SYSTEM PROGRAMMING MODEL The proces
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SYSTEM PROGRAMMING MODEL 3.3 RESET
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INSTRUCTION FORMAT 4.1.1 VEX and th
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INSTRUCTION FORMAT (Bit Position) 7
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INSTRUCTION FORMAT The VEX.vvvv fie
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INSTRUCTION FORMAT 4.1.8 The Third
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INSTRUCTION FORMAT NOTES: 1. If Mod
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INSTRUCTION SET REFERENCE (V)ADDSD
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INSTRUCTION SET REFERENCE register
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INSTRUCTION SET REFERENCE MPSADBW
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INSTRUCTION SET REFERENCE SRC2_BYTE
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INSTRUCTION SET REFERENCE VMPSADBW
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INSTRUCTION SET REFERENCE DEST[79:6
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INSTRUCTION SET REFERENCE Operation
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INSTRUCTION SET REFERENCE PACKSSWB/
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INSTRUCTION SET REFERENCE PACKUSDW
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INSTRUCTION SET REFERENCE TMP[239:2
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INSTRUCTION SET REFERENCE DEST[119:
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INSTRUCTION SET REFERENCE PADDB/PAD
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INSTRUCTION SET REFERENCE PADDQ (Le
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INSTRUCTION SET REFERENCE PADDSB/PA
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INSTRUCTION SET REFERENCE PADDUSB/P
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INSTRUCTION SET REFERENCE PALIGNR
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INSTRUCTION SET REFERENCE PAND —
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INSTRUCTION SET REFERENCE PANDN —
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INSTRUCTION SET REFERENCE PAVGB/PAV
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INSTRUCTION SET REFERENCE PBLENDVB
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INSTRUCTION SET REFERENCE IF (MASK[
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INSTRUCTION SET REFERENCE PBLENDW
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INSTRUCTION SET REFERENCE ELSE DEST
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE PCMPEQQ (
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE PHADDSW
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INSTRUCTION SET REFERENCE PHSUBW/PH
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INSTRUCTION SET REFERENCE PMADDUBSW
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INSTRUCTION SET REFERENCE VPMADDWD
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INSTRUCTION SET REFERENCE VEX.128 e
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INSTRUCTION SET REFERENCE VPMINUD (
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INSTRUCTION SET REFERENCE PMOVMSKB
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INSTRUCTION SET REFERENCE Opcode/ I
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INSTRUCTION SET REFERENCE VPMOVSXWQ
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INSTRUCTION SET REFERENCE PMOVZX
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INSTRUCTION SET REFERENCE Packed_Ze
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE temp13[31
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INSTRUCTION SET REFERENCE PMULHUW
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE PMULLW/PM
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INSTRUCTION SET REFERENCE Temp10[31
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INSTRUCTION SET REFERENCE PMULUDQ
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INSTRUCTION SET REFERENCE POR — B
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INSTRUCTION SET REFERENCE PSADBW
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INSTRUCTION SET REFERENCE PSHUFB
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INSTRUCTION SET REFERENCE PSHUFD
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INSTRUCTION SET REFERENCE PSHUFHW
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INSTRUCTION SET REFERENCE PSHUFLW
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INSTRUCTION SET REFERENCE - FMA VFM
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INSTRUCTION SET REFERENCE - FMA Int
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA } I
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INSTRUCTION SET REFERENCE - FMA ope
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INSTRUCTION SET REFERENCE - FMA VFN
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA Thi
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INSTRUCTION SET REFERENCE - VEX-ENC
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INTEL® TRANSACTIONAL SYNCHRONIZATI
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ADDITIONAL NEW INSTRUCTIONS -------
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ADDITIONAL NEW INSTRUCTIONS • If
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ADDITIONAL NEW INSTRUCTIONS ADCX
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ADDITIONAL NEW INSTRUCTIONS ADOX
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ADDITIONAL NEW INSTRUCTIONS Compati
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ADDITIONAL NEW INSTRUCTIONS Flags A
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ADDITIONAL NEW INSTRUCTIONS STAC—
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OPCODE MAP D The reg field of the M
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OPCODE MAP • A ModR/M byte is req
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OPCODE MAP A.2.5 Superscripts Utili
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OPCODE MAP Table A-2. One-byte Opco
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OPCODE MAP 0 1 2 3 4 5 6 7 Table A-
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OPCODE MAP 8 9 A B C D E F Table A-
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OPCODE MAP 0 Table A-4. Three-byte
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OPCODE MAP 0 66 1 66 2 66 3 4 66 5
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OPCODE MAP A.4 OPCODE EXTENSIONS FO
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OPCODE MAP Opcode Group Mod 7,6 pfx
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OPCODE MAP Table A-8 shows the map
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OPCODE MAP Table A-20 shows the opc
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OPCODE MAP This page was intentiona
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INSTRUCTION SUMMARY VEX.256 Encodin
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INSTRUCTION SUMMARY Note 3: It is e
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INSTRUCTION SUMMARY Table B-2. Prom
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INSTRUCTION SUMMARY Table B-3. VEX-
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INSTRUCTION SUMMARY Opcode Instruct
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SSE extensions flag . . . . . . . .
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SSE extensions CPUID flag . . . . .
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I-6 Ref. # 319433-014
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Intel® Architecture Instruction Set Extensions Programming Reference

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