Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SET REFERENCE
Legacy SSE instructions: In 64-bit mode using a REX prefix in the form of REX.R permits this instruction to access
additional registers (XMM8-XMM15).
128-bit Legacy SSE version: Bits (255:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: Bits (255:128) of the corresponding YMM register are zeroed.
VEX.256 encoded version: Bits (255:128) of the destination stores the shuffled results of the upper 16 bytes of the
source operand using the immediate byte as the order operand.
Note: In VEX encoded versions VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VPSHUFD (VEX.256 encoded version)
DEST[31:0] (SRC[127:0] >> (ORDER[1:0] * 32))[31:0];
DEST[63:32] (SRC[127:0] >> (ORDER[3:2] * 32))[31:0];
DEST[95:64] (SRC[127:0] >> (ORDER[5:4] * 32))[31:0];
DEST[127:96] (SRC[127:0] >> (ORDER[7:6] * 32))[31:0];
DEST[159:128] (SRC[255:128] >> (ORDER[1:0] * 32))[31:0];
DEST[191:160] (SRC[255:128] >> (ORDER[3:2] * 32))[31:0];
DEST[223:192] (SRC[255:128] >> (ORDER[5:4] * 32))[31:0];
DEST[255:224] (SRC[255:128] >> (ORDER[7:6] * 32))[31:0];
VPSHUFD (VEX.128 encoded version)
DEST[31:0] (SRC[127:0] >> (ORDER[1:0] * 32))[31:0];
DEST[63:32] (SRC[127:0] >> (ORDER[3:2] * 32))[31:0];
DEST[95:64] (SRC[127:0] >> (ORDER[5:4] * 32))[31:0];
DEST[127:96] (SRC[127:0] >> (ORDER[7:6] * 32))[31:0];
DEST[VLMAX:128] 0
PSHUFD (128-bit Legacy SSE version)
DEST[31:0] (SRC[255:128] >> (ORDER[1:0] * 32))[31:0];
DEST[63:32] (SRC[255:128] >> (ORDER[3:2] * 32))[31:0];
DEST[95:64] (SRC[255:128] >> (ORDER[5:4] * 32))[31:0];
DEST[127:96] (SRC[255:128] >> (ORDER[7:6] * 32))[31:0];
DEST[VLMAX:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
(V)PSHUFD: __m128i _mm_shuffle_epi32(__m128i a, const int n)
VPSHUFD: __m256i _mm256_shuffle_epi32(__m256i a, const int n)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4
Ref. # 319433-014 5-123