Intel® Architecture Instruction Set Extensions Programming Reference

DEST[191:176] (SRC1 >> (imm[7:6] * 16))[143:128]
DEST[255:192] SRC1[255:192]
VPSHUFLW (VEX.128 encoded version)
DEST[15:0] (SRC1 >> (imm[1:0] *16))[15:0]
DEST[31:16] (SRC1 >> (imm[3:2] * 16))[15:0]
DEST[47:32] (SRC1 >> (imm[5:4] * 16))[15:0]
DEST[63:48] (SRC1 >> (imm[7:6] * 16))[15:0]
DEST[127:64] SRC1[127:64]
DEST[VLMAX:128] 0
PSHUFLW (128-bit Legacy SSE version)
DEST[15:0] (SRC >> (imm[1:0] *16))[15:0]
DEST[31:16] (SRC >> (imm[3:2] * 16))[15:0]
DEST[47:32] (SRC >> (imm[5:4] * 16))[15:0]
DEST[63:48] (SRC >> (imm[7:6] * 16))[15:0]
DEST[127:64] SRC[127:64]
DEST[VLMAX:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
( V)PSHUFLW: __m128i _mm_shufflelo_epi16(__m128i a, const int n)
VPSHUFLW: __m256i _mm256_shufflelo_epi16(__m256i a, const int n)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4
INSTRUCTION SET REFERENCE
Ref. # 319433-014 5-127