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Intel® Architecture Instruction Set Extensions Programming Reference

Intel® Architecture Instruction Set Extensions Programming Reference

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PXOR — Exclusive Or<br />

Opcode/<br />

<strong>Instruction</strong><br />

Description<br />

<strong>Instruction</strong> Operand Encoding<br />

INSTRUCTION SET REFERENCE<br />

Performs a bitwise logical XOR operation on the second source operand and the first source operand and stores the<br />

result in the destination operand. Each bit of the result is set to 1 if the corresponding bits of the first and second<br />

operands differ, otherwise it is set to 0.<br />

Legacy SSE instructions: In 64-bit mode using a REX prefix in the form of REX.R permits this instruction to access<br />

additional registers (XMM8-XMM15).<br />

128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first<br />

source operand and destination operands are XMM registers. Bits (255:128) of the corresponding YMM destination<br />

register remain unchanged.<br />

VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first<br />

source operand and destination operands are XMM registers. Bits (127:128) of the corresponding YMM register are<br />

zeroed.<br />

VEX.256 encoded version: The second source operand is an YMM register or a 256-bit memory location. The first<br />

source operand and destination operands are YMM registers.<br />

Operation<br />

VPXOR (VEX.256 encoded version)<br />

DEST SRC1 XOR SRC2<br />

VPXOR (VEX.128 encoded version)<br />

DEST SRC1 XOR SRC2<br />

DEST[VLMAX:128] 0<br />

PXOR (128-bit Legacy SSE version)<br />

DEST DEST XOR SRC<br />

DEST[VLMAX:128] (Unmodified)<br />

Op/<br />

En<br />

Intel C/C++ Compiler Intrinsic Equivalent<br />

64/3<br />

2-bit<br />

Mode<br />

CPUID<br />

Feature<br />

Flag<br />

(V)PXOR: __m128i _mm_xor_si128 ( __m128i a, __m128i b)<br />

VPXOR: __m256i _mm256_xor_si256 ( __m256i a, __m256i b)<br />

Description<br />

66 0F EF /r A V/V SSE2 Bitwise XOR of xmm2/m128 and xmm1.<br />

PXOR xmm1, xmm2/m128<br />

VEX.NDS.128.66.0F.WIG EF /r B V/V AVX Bitwise XOR of xmm3/m128 and xmm2.<br />

VPXOR xmm1, xmm2, xmm3/m128<br />

VEX.NDS.256.66.0F.WIG EF /r B V/V AVX2 Bitwise XOR of ymm3/m256 and ymm2.<br />

VPXOR ymm1, ymm2, ymm3/m256<br />

Op/En Operand 1 Operand 2 Operand 3 Operand 4<br />

A ModRM:reg (r, w) ModRM:r/m (r) NA NA<br />

B ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA<br />

Ref. # 319433-014 5-171

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