Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SET REFERENCE
VPMINUD (VEX.256 encoded version)
VPMINUD instruction for 128-bit operands:
IF SRC1[31:0] < SRC2[31:0] THEN
DEST[31:0] SRC1[31:0];
ELSE
DEST[31:0] SRC2[31:0]; FI;
(* Repeat operation for 2nd through 7th dwords in source and destination operands *)
IF SRC1[255:224] < SRC2[255:224] THEN
DEST[255:224] SRC1[255:224];
ELSE
DEST[255:224] SRC2[255:224]; FI;
Intel C/C++ Compiler Intrinsic Equivalent
(V)PMINUB: __m128i _mm_min_epu8 ( __m128i a, __m128i b)
(V)PMINUW: __m128i _mm_min_epu16 ( __m128i a, __m128i b);
(V)PMINUD: __m128i _mm_min_epu32 ( __m128i a, __m128i b);
VPMINUB: __m256i _mm256_min_epu8 ( __m256i a, __m256i b)
VPMINUW: __m256i _mm256_min_epu16 ( __m256i a, __m256i b);
VPMINUD: __m256i _mm256_min_epu32 ( __m256i a, __m256i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4
5-86 Ref. # 319433-014