Intel® Architecture Instruction Set Extensions Programming Reference

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$Intel® Math Kernel Library (Intel® MKL) 11.0 Release Notes$

$Intel® Math Kernel Library 11.0 Support for Intel® Xeon Phi ...$

DEST[223:208] SRC2[239:224] DEST[239:224] SRC1[255:240] DEST[255:240] SRC2[255:240] INTERLEAVE_HIGH_WORDS (SRC1, SRC2) DEST[15:0] SRC1[79:64] DEST[31:16] SRC2[79:64] DEST[47:32] SRC1[95:80] DEST[63:48] SRC2[95:80] DEST[79:64] SRC1[111:96] DEST[95:80] SRC2[111:96] DEST[111:96] SRC1[127:112] DEST[127:112] SRC2[127:112] INTERLEAVE_HIGH_DWORDS_256b(SRC1, SRC2) DEST[31:0] SRC1[95:64] DEST[63:32] SRC2[95:64] DEST[95:64] SRC1[127:96] DEST[127:96] SRC2[127:96] DEST[159:128] SRC1[223:192] DEST[191:160] SRC2[223:192] DEST[223:192] SRC1[255:224] DEST[255:224] SRC2[255:224] INTERLEAVE_HIGH_DWORDS(SRC1, SRC2) DEST[31:0] SRC1[95:64] DEST[63:32] SRC2[95:64] DEST[95:64] SRC1[127:96] DEST[127:96] SRC2[127:96] INTERLEAVE_HIGH_QWORDS_256b(SRC1, SRC2) DEST[63:0] SRC1[127:64] DEST[127:64] SRC2[127:64] DEST[191:128] SRC1[255:192] DEST[255:192] SRC2[255:192] INTERLEAVE_HIGH_QWORDS(SRC1, SRC2) DEST[63:0] SRC1[127:64] DEST[127:64] SRC2[127:64] PUNPCKHBW (128-bit Legacy SSE Version) DEST[127:0] INTERLEAVE_HIGH_BYTES(DEST, SRC) DEST[255:127] (Unmodified) VPUNPCKHBW (VEX.128 encoded version) DEST[127:0] INTERLEAVE_HIGH_BYTES(SRC1, SRC2) DEST[255:127] 0 VPUNPCKHBW (VEX.256 encoded version) DEST[255:0] INTERLEAVE_HIGH_BYTES_256b(SRC1, SRC2) PUNPCKHWD (128-bit Legacy SSE Version) DEST[127:0] INTERLEAVE_HIGH_WORDS(DEST, SRC) DEST[255:127] (Unmodified) INSTRUCTION SET REFERENCE Ref. # 319433-014 5-163
INSTRUCTION SET REFERENCE VPUNPCKHWD (VEX.128 encoded version) DEST[127:0] INTERLEAVE_HIGH_WORDS(SRC1, SRC2) DEST[255:127] 0 VPUNPCKHWD (VEX.256 encoded version) DEST[255:0] INTERLEAVE_HIGH_WORDS_256b(SRC1, SRC2) PUNPCKHDQ (128-bit Legacy SSE Version) DEST[127:0] INTERLEAVE_HIGH_DWORDS(DEST, SRC) DEST[255:127] (Unmodified) VPUNPCKHDQ (VEX.128 encoded version) DEST[127:0] INTERLEAVE_HIGH_DWORDS(SRC1, SRC2) DEST[255:127] 0 VPUNPCKHDQ (VEX.256 encoded version) DEST[255:0] INTERLEAVE_HIGH_DWORDS_256b(SRC1, SRC2) PUNPCKHQDQ (128-bit Legacy SSE Version) DEST[127:0] INTERLEAVE_HIGH_QWORDS(DEST, SRC) DEST[255:127] (Unmodified) VPUNPCKHQDQ (VEX.128 encoded version) DEST[127:0] INTERLEAVE_HIGH_QWORDS(SRC1, SRC2) DEST[255:127] 0 VPUNPCKHQDQ (VEX.256 encoded version) DEST[255:0] INTERLEAVE_HIGH_QWORDS_256(SRC1, SRC2) Intel C/C++ Compiler Intrinsic Equivalent (V)PUNPCKHBW: __m128i _mm_unpackhi_epi8(__m128i m1, __m128i m2) VPUNPCKHBW: __m256i _mm256_unpackhi_epi8(__m256i m1, __m256i m2) (V)PUNPCKHWD: __m128i _mm_unpackhi_epi16(__m128i m1,__m128i m2) VPUNPCKHWD: __m256i _mm256_unpackhi_epi16(__m256i m1,__m256i m2) (V)PUNPCKHDQ: __m128i _mm_unpackhi_epi32(__m128i m1, __m128i m2) VPUNPCKHDQ: __m256i _mm256_unpackhi_epi32(__m256i m1, __m256i m2) (V)PUNPCKHQDQ: __m128i _mm_unpackhi_epi64 ( __m128i a, __m128i b) VPUNPCKHQDQ: __m256i _mm256_unpackhi_epi64 ( __m256i a, __m256i b) SIMD Floating-Point Exceptions None Other Exceptions See Exceptions Type 4 5-164 Ref. # 319433-014
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Intel® Architecture Instruction Se
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CONTENTS CHAPTER 1 INTEL® ADVANCED
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PANDN — Logical AND NOT . . . . .
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BZHI — Zero High Bits Starting wi
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TABLES 2-1 Rounding behavior of Zer
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FIGURES Figure 2-1. General Procedu
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INTEL® ADVANCED VECTOR EXTENSIONS
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APPLICATION PROGRAMMING MODEL Prior
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APPLICATION PROGRAMMING MODEL } and
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APPLICATION PROGRAMMING MODEL Scala
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APPLICATION PROGRAMMING MODEL x (mu
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APPLICATION PROGRAMMING MODEL Instr
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APPLICATION PROGRAMMING MODEL Table
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APPLICATION PROGRAMMING MODEL Excep
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APPLICATION PROGRAMMING MODEL 2.7.2
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APPLICATION PROGRAMMING MODEL EAX 3
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APPLICATION PROGRAMMING MODEL • T
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APPLICATION PROGRAMMING MODEL How B
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APPLICATION PROGRAMMING MODEL
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APPLICATION PROGRAMMING MODEL EAX[1
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APPLICATION PROGRAMMING MODEL EBX
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SYSTEM PROGRAMMING MODEL • Verify
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SYSTEM PROGRAMMING MODEL The proces
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SYSTEM PROGRAMMING MODEL 3.3 RESET
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INSTRUCTION FORMAT 4.1.1 VEX and th
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INSTRUCTION FORMAT (Bit Position) 7
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INSTRUCTION FORMAT The VEX.vvvv fie
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INSTRUCTION FORMAT 4.1.8 The Third
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INSTRUCTION FORMAT NOTES: 1. If Mod
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INSTRUCTION SET REFERENCE (V)ADDSD
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INSTRUCTION SET REFERENCE register
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INSTRUCTION SET REFERENCE MPSADBW
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INSTRUCTION SET REFERENCE SRC2_BYTE
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INSTRUCTION SET REFERENCE VMPSADBW
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INSTRUCTION SET REFERENCE DEST[79:6
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INSTRUCTION SET REFERENCE Operation
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INSTRUCTION SET REFERENCE PACKSSWB/
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INSTRUCTION SET REFERENCE PACKUSDW
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INSTRUCTION SET REFERENCE TMP[239:2
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INSTRUCTION SET REFERENCE DEST[119:
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INSTRUCTION SET REFERENCE PADDB/PAD
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INSTRUCTION SET REFERENCE PADDQ (Le
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INSTRUCTION SET REFERENCE PADDSB/PA
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INSTRUCTION SET REFERENCE PADDUSB/P
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INSTRUCTION SET REFERENCE PALIGNR
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INSTRUCTION SET REFERENCE PAND —
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INSTRUCTION SET REFERENCE PANDN —
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INSTRUCTION SET REFERENCE PAVGB/PAV
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INSTRUCTION SET REFERENCE PBLENDVB
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INSTRUCTION SET REFERENCE IF (MASK[
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INSTRUCTION SET REFERENCE PBLENDW
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INSTRUCTION SET REFERENCE ELSE DEST
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE PCMPEQQ (
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE PHADDSW
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INSTRUCTION SET REFERENCE PHSUBW/PH
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INSTRUCTION SET REFERENCE PMADDUBSW
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INSTRUCTION SET REFERENCE VPMADDWD
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INSTRUCTION SET REFERENCE VEX.128 e
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INSTRUCTION SET REFERENCE VPMINUD (
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INSTRUCTION SET REFERENCE PMOVMSKB
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INSTRUCTION SET REFERENCE Opcode/ I
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INSTRUCTION SET REFERENCE VPMOVSXWQ
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INSTRUCTION SET REFERENCE PMOVZX
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INSTRUCTION SET REFERENCE Packed_Ze
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE temp13[31
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INSTRUCTION SET REFERENCE PMULHUW
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE PMULLW/PM
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Page 201 and 202: INSTRUCTION SET REFERENCE POR — B
Page 203 and 204: INSTRUCTION SET REFERENCE PSADBW
Page 205 and 206: INSTRUCTION SET REFERENCE PSHUFB
Page 207 and 208: INSTRUCTION SET REFERENCE PSHUFD
Page 209 and 210: INSTRUCTION SET REFERENCE PSHUFHW
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Page 213 and 214: INSTRUCTION SET REFERENCE PSIGNB/PS
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Page 217 and 218: INSTRUCTION SET REFERENCE PSLLDQ
Page 219 and 220: INSTRUCTION SET REFERENCE PSLLW/PSL
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Page 223 and 224: INSTRUCTION SET REFERENCE PSLLD (xm
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Page 229 and 230: INSTRUCTION SET REFERENCE PSRLDQ
Page 231 and 232: INSTRUCTION SET REFERENCE PSRLW/PSR
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Page 235 and 236: INSTRUCTION SET REFERENCE VPSRLQ (x
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Page 241 and 242: INSTRUCTION SET REFERENCE PSUBSB/PS
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Page 245 and 246: INSTRUCTION SET REFERENCE PUNPCKHBW
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Page 289 and 290: INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE This page
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INSTRUCTION SET REFERENCE - FMA VFM
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INSTRUCTION SET REFERENCE - FMA For
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INSTRUCTION SET REFERENCE - FMA sou
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INSTRUCTION SET REFERENCE - FMA Int
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA } I
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INSTRUCTION SET REFERENCE - FMA ope
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INSTRUCTION SET REFERENCE - FMA VFN
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA Thi
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INSTRUCTION SET REFERENCE - VEX-ENC
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INTEL® TRANSACTIONAL SYNCHRONIZATI
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ADDITIONAL NEW INSTRUCTIONS -------
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ADDITIONAL NEW INSTRUCTIONS • If
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ADDITIONAL NEW INSTRUCTIONS ADCX
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ADDITIONAL NEW INSTRUCTIONS ADOX
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ADDITIONAL NEW INSTRUCTIONS Compati
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ADDITIONAL NEW INSTRUCTIONS Flags A
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ADDITIONAL NEW INSTRUCTIONS STAC—
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OPCODE MAP D The reg field of the M
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OPCODE MAP • A ModR/M byte is req
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OPCODE MAP A.2.5 Superscripts Utili
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OPCODE MAP Table A-2. One-byte Opco
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OPCODE MAP 0 1 2 3 4 5 6 7 Table A-
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OPCODE MAP 8 9 A B C D E F Table A-
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OPCODE MAP 0 Table A-4. Three-byte
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OPCODE MAP 0 66 1 66 2 66 3 4 66 5
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OPCODE MAP A.4 OPCODE EXTENSIONS FO
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OPCODE MAP Opcode Group Mod 7,6 pfx
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OPCODE MAP Table A-8 shows the map
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OPCODE MAP Table A-20 shows the opc
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OPCODE MAP This page was intentiona
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INSTRUCTION SUMMARY VEX.256 Encodin
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INSTRUCTION SUMMARY Note 3: It is e
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INSTRUCTION SUMMARY Table B-2. Prom
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INSTRUCTION SUMMARY Table B-3. VEX-
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INSTRUCTION SUMMARY Opcode Instruct
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SSE extensions flag . . . . . . . .
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SSE extensions CPUID flag . . . . .
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I-6 Ref. # 319433-014
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Intel® Architecture Instruction Set Extensions Programming Reference

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