Intel® Architecture Instruction Set Extensions Programming Reference

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$Intel® Math Kernel Library (Intel® MKL) 11.0 Release Notes$

$Intel® Math Kernel Library 11.0 Support for Intel® Xeon Phi ...$

Table B-2. Promoted Vector Integer SIMD Instructions in AVX2 VEX.256 Encoding VEX.128 Encoding Group Instruction AVX2 AVX PSRLD AVX2 AVX PSRLQ AVX2 AVX PADDQ AVX2 AVX PMULLW AVX2 AVX PMOVMSKB AVX2 AVX PSUBUSB AVX2 AVX PSUBUSW AVX2 AVX PMINUB AVX2 AVX PAND AVX2 AVX PADDUSB AVX2 AVX PADDUSW AVX2 AVX PMAXUB AVX2 AVX PANDN AVX2 AVX YY 0F EX PAVGB AVX2 AVX PSRAW AVX2 AVX PSRAD AVX2 AVX PAVGW AVX2 AVX PMULHUW AVX2 AVX PMULHW AVX AVX MOVNTDQ AVX2 AVX PSUBSB AVX2 AVX PSUBSW AVX2 AVX PMINSW AVX2 AVX POR AVX2 AVX PADDSB AVX2 AVX PADDSW AVX2 AVX PMAXSW AVX2 AVX PXOR AVX AVX YY 0F FX LDDQU AVX2 AVX PSLLW AVX2 AVX PSLLD AVX2 AVX PSLLQ AVX2 AVX PMULUDQ AVX2 AVX PMADDWD AVX2 AVX PSADBW AVX2 AVX PSUBB AVX2 AVX PSUBW AVX2 AVX PSUBD INSTRUCTION SUMMARY Ref. # 319433-014 B-9
INSTRUCTION SUMMARY Table B-2. Promoted Vector Integer SIMD Instructions in AVX2 VEX.256 Encoding VEX.128 Encoding Group Instruction AVX2 AVX PSUBQ AVX2 AVX PADDB AVX2 AVX PADDW AVX2 AVX PADDD AVX2 AVX SSSE3 PHADDW AVX2 AVX PHADDSW AVX2 AVX PHADDD AVX2 AVX PHSUBW AVX2 AVX PHSUBSW AVX2 AVX PHSUBD AVX2 AVX PMADDUBSW AVX2 AVX PALIGNR AVX2 AVX PSHUFB AVX2 AVX PMULHRSW AVX2 AVX PSIGNB AVX2 AVX PSIGNW AVX2 AVX PSIGND AVX2 AVX PABSB AVX2 AVX PABSW AVX2 AVX PABSD AVX2 AVX MOVNTDQA AVX2 AVX MPSADBW AVX2 AVX PACKUSDW AVX2 AVX PBLENDVB AVX2 AVX PBLENDW AVX2 AVX PCMPEQQ no AVX PEXTRD no AVX PEXTRQ no AVX PEXTRB no AVX PEXTRW no AVX PHMINPOSUW no AVX PINSRB no AVX PINSRD no AVX PINSRQ AVX2 AVX PMAXSB AVX2 AVX PMAXSD AVX2 AVX PMAXUD AVX2 AVX PMAXUW B-10 Ref. # 319433-014
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Intel® Architecture Instruction Se
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CONTENTS CHAPTER 1 INTEL® ADVANCED
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PANDN — Logical AND NOT . . . . .
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BZHI — Zero High Bits Starting wi
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TABLES 2-1 Rounding behavior of Zer
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FIGURES Figure 2-1. General Procedu
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INTEL® ADVANCED VECTOR EXTENSIONS
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APPLICATION PROGRAMMING MODEL Prior
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APPLICATION PROGRAMMING MODEL } and
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APPLICATION PROGRAMMING MODEL Scala
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APPLICATION PROGRAMMING MODEL x (mu
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APPLICATION PROGRAMMING MODEL Instr
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APPLICATION PROGRAMMING MODEL Table
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APPLICATION PROGRAMMING MODEL Excep
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APPLICATION PROGRAMMING MODEL 2.7.2
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APPLICATION PROGRAMMING MODEL EAX 3
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APPLICATION PROGRAMMING MODEL • T
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APPLICATION PROGRAMMING MODEL How B
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APPLICATION PROGRAMMING MODEL
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APPLICATION PROGRAMMING MODEL EAX[1
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APPLICATION PROGRAMMING MODEL EBX
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SYSTEM PROGRAMMING MODEL • Verify
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SYSTEM PROGRAMMING MODEL The proces
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SYSTEM PROGRAMMING MODEL 3.3 RESET
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INSTRUCTION FORMAT 4.1.1 VEX and th
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INSTRUCTION FORMAT (Bit Position) 7
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INSTRUCTION FORMAT The VEX.vvvv fie
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INSTRUCTION FORMAT 4.1.8 The Third
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INSTRUCTION FORMAT NOTES: 1. If Mod
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INSTRUCTION SET REFERENCE (V)ADDSD
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INSTRUCTION SET REFERENCE register
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INSTRUCTION SET REFERENCE MPSADBW
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INSTRUCTION SET REFERENCE SRC2_BYTE
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INSTRUCTION SET REFERENCE VMPSADBW
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INSTRUCTION SET REFERENCE DEST[79:6
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INSTRUCTION SET REFERENCE Operation
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INSTRUCTION SET REFERENCE PACKSSWB/
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INSTRUCTION SET REFERENCE PACKUSDW
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INSTRUCTION SET REFERENCE TMP[239:2
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INSTRUCTION SET REFERENCE DEST[119:
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INSTRUCTION SET REFERENCE PADDB/PAD
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INSTRUCTION SET REFERENCE PADDQ (Le
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INSTRUCTION SET REFERENCE PADDSB/PA
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INSTRUCTION SET REFERENCE PADDUSB/P
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INSTRUCTION SET REFERENCE PALIGNR
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INSTRUCTION SET REFERENCE PAND —
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INSTRUCTION SET REFERENCE PANDN —
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INSTRUCTION SET REFERENCE PAVGB/PAV
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INSTRUCTION SET REFERENCE PBLENDVB
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INSTRUCTION SET REFERENCE IF (MASK[
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INSTRUCTION SET REFERENCE PBLENDW
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INSTRUCTION SET REFERENCE ELSE DEST
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE PCMPEQQ (
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE PHADDSW
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INSTRUCTION SET REFERENCE PHSUBW/PH
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INSTRUCTION SET REFERENCE PMADDUBSW
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INSTRUCTION SET REFERENCE VPMADDWD
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INSTRUCTION SET REFERENCE VEX.128 e
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INSTRUCTION SET REFERENCE VPMINUD (
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INSTRUCTION SET REFERENCE PMOVMSKB
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INSTRUCTION SET REFERENCE Opcode/ I
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INSTRUCTION SET REFERENCE VPMOVSXWQ
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INSTRUCTION SET REFERENCE PMOVZX
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INSTRUCTION SET REFERENCE Packed_Ze
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE temp13[31
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INSTRUCTION SET REFERENCE PMULHUW
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INSTRUCTION SET REFERENCE PMULLW/PM
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INSTRUCTION SET REFERENCE Temp10[31
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INSTRUCTION SET REFERENCE PMULUDQ
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INSTRUCTION SET REFERENCE POR — B
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INSTRUCTION SET REFERENCE PSADBW
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INSTRUCTION SET REFERENCE PSHUFB
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INSTRUCTION SET REFERENCE PSHUFD
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INSTRUCTION SET REFERENCE PSHUFHW
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INSTRUCTION SET REFERENCE PSHUFLW
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INSTRUCTION SET REFERENCE PSIGNB/PS
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INSTRUCTION SET REFERENCE DEST[255.
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INSTRUCTION SET REFERENCE PSLLDQ
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INSTRUCTION SET REFERENCE PSLLW/PSL
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INSTRUCTION SET REFERENCE PSLLD (xm
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INSTRUCTION SET REFERENCE PSRAW/PSR
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INSTRUCTION SET REFERENCE COUNT 31
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INSTRUCTION SET REFERENCE PSRLDQ
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INSTRUCTION SET REFERENCE PSRLW/PSR
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INSTRUCTION SET REFERENCE FI; DEST[
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INSTRUCTION SET REFERENCE VPSRLQ (x
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INSTRUCTION SET REFERENCE PSUBSB/PS
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INSTRUCTION SET REFERENCE PSUBUSB/P
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INSTRUCTION SET REFERENCE PUNPCKHBW
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INSTRUCTION SET REFERENCE VPUNPCKHW
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INSTRUCTION SET REFERENCE Instructi
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INSTRUCTION SET REFERENCE INTERLEAV
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INSTRUCTION SET REFERENCE VPUNPCKLD
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INSTRUCTION SET REFERENCE SIMD Floa
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INSTRUCTION SET REFERENCE VBROADCAS
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INSTRUCTION SET REFERENCE VPBLENDD
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INSTRUCTION SET REFERENCE VPBROADCA
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INSTRUCTION SET REFERENCE VPERMPD
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INSTRUCTION SET REFERENCE VPERMQ
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INSTRUCTION SET REFERENCE VINSERTI1
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INSTRUCTION SET REFERENCE The secon
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INSTRUCTION SET REFERENCE VPSLLVD/V
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE VPSRAVD (
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INSTRUCTION SET REFERENCE VPSRLVD (
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE This page
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INSTRUCTION SET REFERENCE - FMA VFM
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INSTRUCTION SET REFERENCE - FMA For
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INSTRUCTION SET REFERENCE - FMA sou
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INSTRUCTION SET REFERENCE - FMA Int
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA } I
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INSTRUCTION SET REFERENCE - FMA ope
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INSTRUCTION SET REFERENCE - FMA VFN
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA Thi
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INSTRUCTION SET REFERENCE - VEX-ENC
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INTEL® TRANSACTIONAL SYNCHRONIZATI
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Page 407 and 408: ADDITIONAL NEW INSTRUCTIONS -------
Page 409 and 410: ADDITIONAL NEW INSTRUCTIONS • If
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Page 415 and 416: ADDITIONAL NEW INSTRUCTIONS Compati
Page 417 and 418: ADDITIONAL NEW INSTRUCTIONS Flags A
Page 419 and 420: ADDITIONAL NEW INSTRUCTIONS STAC—
Page 421 and 422: OPCODE MAP D The reg field of the M
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Page 429 and 430: OPCODE MAP 0 1 2 3 4 5 6 7 Table A-
Page 431 and 432: OPCODE MAP 8 9 A B C D E F Table A-
Page 433 and 434: OPCODE MAP 0 Table A-4. Three-byte
Page 435 and 436: OPCODE MAP 0 66 1 66 2 66 3 4 66 5
Page 437 and 438: OPCODE MAP A.4 OPCODE EXTENSIONS FO
Page 439 and 440: OPCODE MAP Opcode Group Mod 7,6 pfx
Page 441 and 442: OPCODE MAP Table A-8 shows the map
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Page 451 and 452: INSTRUCTION SUMMARY VEX.256 Encodin
Page 457: INSTRUCTION SUMMARY Note 3: It is e
Page 461 and 462: INSTRUCTION SUMMARY Table B-3. VEX-
Page 463 and 464: INSTRUCTION SUMMARY Opcode Instruct
Page 473 and 474: SSE extensions flag . . . . . . . .
Page 475 and 476: SSE extensions CPUID flag . . . . .
Page 477: I-6 Ref. # 319433-014
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Intel® Architecture Instruction Set Extensions Programming Reference

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