Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SET REFERENCE
software must encode the instruction with VEX.L = 0. The processor will treat the opcode byte encoded
with VEX.L= 1 by causing an #UD exception (e.g. VMOVLPS).
• If VEX.LIG is present in the opcode column: The VEX.L value is ignored. This generally applies to VEXencoded
scalar SIMD floating-point instructions. Scalar SIMD floating-point instruction can be distinguished
from the mnemonic of the instruction. Generally, the last two letters of the instruction
mnemonic would be either “SS“, “SD“, or “SI“ for SIMD floating-point conversion instructions.
• If VEX.LZ is present in the opcode column: The VEX.L must be encoded to be 0B, an #UD occurs if
VEX.L is not zero.
— 66,F2,F3: The presence or absence of these value maps to the VEX.pp field encodings. If absent, this
corresponds to VEX.pp=00B. If present, the corresponding VEX.pp value affects the “opcode” byte in the
same way as if a SIMD prefix (66H, F2H or F3H) does to the ensuing opcode byte. Thus a non-zero encoding
of VEX.pp may be considered as an implied 66H/F2H/F3H prefix. The VEX.pp field may be encoded using
either the 2-byte or 3-byte form of the VEX prefix.
— 0F,0F3A,0F38: The presence maps to a valid encoding of the VEX.mmmmm field. Only three encoded
values of VEX.mmmmm are defined as valid, corresponding to the escape byte sequence of 0FH, 0F3AH
and 0F38H. The effect of a valid VEX.mmmmm encoding on the ensuing opcode byte is same as if the
corresponding escape byte sequence on the ensuing opcode byte for non-VEX encoded instructions. Thus a
valid encoding of VEX.mmmmm may be consider as an implies escape byte sequence of either 0FH, 0F3AH
or 0F38H. The VEX.mmmmm field must be encoded using the 3-byte form of VEX prefix.
— 0F,0F3A,0F38 and 2-byte/3-byte VEX. The presence of 0F3A and 0F38 in the opcode column implies
that opcode can only be encoded by the three-byte form of VEX. The presence of 0F in the opcode column
does not preclude the opcode to be encoded by the two-byte of VEX if the semantics of the opcode does not
require any subfield of VEX not present in the two-byte form of the VEX prefix.
— W0: VEX.W=0.
— W1: VEX.W=1.
— The presence of W0/W1 in the opcode column applies to two situations: (a) it is treated as an extended
opcode bit, (b) the instruction semantics support an operand size promotion to 64-bit of a general-purpose
register operand or a 32-bit memory operand. The presence of W1 in the opcode column implies the opcode
must be encoded using the 3-byte form of the VEX prefix. The presence of W0 in the opcode column does
not preclude the opcode to be encoded using the C5H form of the VEX prefix, if the semantics of the opcode
does not require other VEX subfields not present in the two-byte form of the VEX prefix. Please see Section
4.1.4 on the subfield definitions within VEX.
— WIG: If WIG is present, the instruction may be encoded using the C5H form (if VEX.mmmmm is not
required); or when using the C4H form of VEX prefix, VEX.W value is ignored.
• opcode: Instruction opcode.
• /r — Indicates that the ModR/M byte of the instruction contains a register operand and an r/m operand.
• ib: A 1-byte immediate operand to the instruction that follows the opcode, ModR/M bytes or scale/indexing
bytes.
• /is4: An 8-bit immediate byte is present specifying a source register in imm[7:4] and containing an
instruction-specific payload in imm[3:0].
• In general, the encoding of the VEX.R, VEX.X, and VEX.B fields are not shown explicitly in the opcode column.
The encoding scheme of VEX.R, VEX.X, and VEX.B fields must follow the rules defined in Section 4.1.4.
5.1.3 Instruction Column in the Instruction Summary Table
• ymm — A YMM register. The 256-bit YMM registers are: YMM0 through YMM7; YMM8 through YMM15 are
available in 64-bit mode.
• m256 — A 32-byte operand in memory. This nomenclature is used only with AVX and FMA instructions.
• vm32x,vm32y — A vector array of memory operands specified using VSIB memory addressing. The array of
memory addresses are specified using a common base register, a constant scale factor, and a vector index
Ref. # 319433-014 5-3