Intel® Architecture Instruction Set Extensions Programming Reference

PMULDQ — Multiply Packed Doubleword Integers
Opcode/
Instruction
Description
Op/
En
64/32
-bit
Mode
CPUID
Feature
Flag
Description
Instruction Operand Encoding
INSTRUCTION SET REFERENCE
66 0F 38 28 /r A V/V SSE4_1 Multiply packed signed doubleword integers in xmm1 by packed
PMULDQ xmm1, xmm2/m128
signed doubleword integers in xmm2/m128, and store the quadword
results in xmm1.
VEX.NDS.128.66.0F38.WIG 28 /r B V/V AVX Multiply packed signed doubleword integers in xmm2 by packed
VPMULDQ xmm1, xmm2,
xmm3/m128
signed doubleword integers in xmm3/m128, and store the quadword
results in xmm1.
VEX.NDS.256.66.0F38.WIG 28 /r B V/V AVX2 Multiply packed signed doubleword integers in ymm2 by packed
VPMULDQ ymm1, ymm2,
ymm3/m256
signed doubleword integers in ymm3/m256, and store the quadword
results in ymm1.
Op/En Operand 1 Operand 2 Operand 3 Operand 4
A ModRM:reg (r, w) ModRM:r/m (r) NA NA
B ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA
Multiplies the first source operand by the second source operand and stores the result in the destination operand.
For PMULDQ and VPMULDQ (VEX.128 encoded version), the second source operand is two packed signed doubleword
integers stored in the first (low) and third doublewords of an XMM register or a 128-bit memory location. The
first source operand is two packed signed doubleword integers stored in the first and third doublewords of an XMM
register. The destination contains two packed signed quadword integers stored in an XMM register. For 128-bit
memory operands, 128 bits are fetched from memory, but only the first and third doublewords are used in the
computation.
For VPMULDQ (VEX.256 encoded version), the second source operand is four packed signed doubleword integers
stored in the first (low), third, fifth and seventh doublewords of an YMM register or a 256-bit memory location. The
first source operand is four packed signed doubleword integers stored in the first, third, fifth and seventh doublewords
of an XMM register. The destination contains four packed signed quadword integers stored in an YMM
register. For 256-bit memory operands, 256 bits are fetched from memory, but only the first, third, fifth and
seventh doublewords are used in the computation.
When a quadword result is too large to be represented in 64 bits (overflow), the result is wrapped around and the
low 64 bits are written to the destination element (that is, the carry is ignored).
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (255:128) of the corresponding YMM destination
register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (255:128) of the corresponding YMM register are
zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
Ref. # 319433-014 5-99