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Intel® Architecture Instruction Set Extensions Programming Reference

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APPLICATION PROGRAMMING MODEL<br />

Table 2-23. Information Returned by CPUID <strong>Instruction</strong>(Continued)<br />

Initial EAX<br />

Value Information Provided about the Processor<br />

EDX Bits 31- 0: x2APIC ID the current logical processor.<br />

NOTES:<br />

* Software should use this field (EAX[4:0]) to enumerate processor topology of the system.<br />

** Software must not use EBX[15:0] to enumerate processor topology of the system. This value in<br />

this field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual number of logical<br />

processors available to BIOS/OS/Applications may be different from the value of EBX[15:0], depending<br />

on software and platform hardware configurations.<br />

*** The value of the “level type” field is not related to level numbers in any way, higher “level type”<br />

values do not mean higher levels. Level type field has the following encoding:<br />

0: invalid<br />

1: SMT<br />

2: Core<br />

3-255: Reserved<br />

Processor Extended State Enumeration Main Leaf (EAX = 0DH, ECX = 0)<br />

0DH NOTES:<br />

Leaf 0DH main leaf (ECX = 0).<br />

EAX Bits 31-00: Reports the valid bit fields of the lower 32 bits of the XFEATURE_ENABLED_MASK register.<br />

If a bit is 0, the corresponding bit field in XFEATURE_ENABLED_MASK is reserved.<br />

Bit 00: legacy x87<br />

Bit 01: 128-bit SSE<br />

Bit 02: 256-bit AVX<br />

EBX Bits 31-00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) required by<br />

enabled features in XCR0. May be different than ECX if some features at the end of the XSAVE save<br />

area are not enabled.<br />

ECX Bit 31-00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) of the<br />

XSAVE/XRSTOR save area required by all supported features in the processor, i.e all the valid bit<br />

fields in XCR0.<br />

EDX Bit 31-0: Reports the valid bit fields of the upper 32 bits of the XFEATURE_ENABLED_MASK register<br />

(XCR0). If a bit is 0, the corresponding bit field in XCR0 is reserved<br />

Processor Extended State Enumeration Sub-leaf (EAX = 0DH, ECX = 1)<br />

EAX<br />

EBX<br />

ECX<br />

EDX<br />

Bit 00: XSAVEOPT is available;<br />

Bits 31-1: Reserved<br />

Reserved<br />

Reserved<br />

Reserved<br />

Processor Extended State Enumeration Sub-leaves (EAX = 0DH, ECX = n, n > 1)<br />

0DH NOTES:<br />

Leaf 0DH output depends on the initial value in ECX.<br />

If ECX contains an invalid sub leaf index, EAX/EBX/ECX/EDX return 0.<br />

Each valid sub-leaf index maps to a valid bit in the XCR0 register starting at bit position 2<br />

EAX Bits 31-0: The size in bytes (from the offset specified in EBX) of the save area for an extended state<br />

feature associated with a valid sub-leaf index, n. This field reports 0 if the sub-leaf index, n, is<br />

invalid*.<br />

EBX Bits 31-0: The offset in bytes of this extended state component’s save area from the beginning of<br />

the XSAVE/XRSTOR area.<br />

This field reports 0 if the sub-leaf index, n, is invalid*.<br />

2-32 Ref. # 319433-014

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