Intel® Architecture Instruction Set Extensions Programming Reference

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$Intel® Math Kernel Library (Intel® MKL) 11.0 Release Notes$

$Intel® Math Kernel Library 11.0 Support for Intel® Xeon Phi ...$

PABSB/PABSW/PABSD — Packed Absolute Value Opcode/ <strong>Instruction</strong> Description Op/ En 64/32bit Mode CPUID Feature Flag Description <strong>Instruction</strong> Operand Encoding INSTRUCTION SET REFERENCE 66 0F 38 1C /r A V/V SSSE3 Compute the absolute value of bytes in xmm2/m128 and store UNSIGNED result in xmm1. PABSB xmm1, xmm2/m128 66 0F 38 1D /r A V/V SSSE3 Compute the absolute value of 16-bit integers in xmm2/m128 and store UNSIGNED result in xmm1. PABSW xmm1, xmm2/m128 66 0F 38 1E /r A V/V SSSE3 Compute the absolute value of 32-bit integers in xmm2/m128 and store UNSIGNED result in xmm1. PABSD xmm1, xmm2/m128 VEX.128.66.0F38.WIG 1C /r A V/V AVX Compute the absolute value of bytes in xmm2/m128 and store UNSIGNED result in xmm1. VPABSB xmm1, xmm2/m128 VEX.128.66.0F38.WIG 1D /r A V/V AVX Compute the absolute value of 16-bit integers in xmm2/m128 and store UNSIGNED result in xmm1. VPABSW xmm1, xmm2/m128 VEX.128.66.0F38.WIG 1E /r A V/V AVX Compute the absolute value of 32-bit integers in xmm2/m128 and store UNSIGNED result in xmm1. VPABSD xmm1, xmm2/m128 VEX.256.66.0F38.WIG 1C /r A V/V AVX2 Compute the absolute value of bytes in ymm2/m256 and store UNSIGNED result in ymm1. VPABSB ymm1, ymm2/m256 VEX.256.66.0F38.WIG 1D /r A V/V AVX2 Compute the absolute value of 16-bit integers in ymm2/m256 and store UNSIGNED result in ymm1. VPABSW ymm1, ymm2/m256 VEX.256.66.0F38.WIG 1E /r A V/V AVX2 Compute the absolute value of 32-bit integers in ymm2/m256 and store UNSIGNED result in ymm1. VPABSD ymm1, ymm2/m256 Op/En Operand 1 Operand 2 Operand 3 Operand 4 A ModRM:reg (w) ModRM:r/m (r) NA NA (V)PABSB/W/D computes the absolute value of each data element of the source operand (the second operand) and stores the UNSIGNED results in the destination operand (the first operand). (V)PABSB operates on signed bytes, (V)PABSW operates on 16-bit words, and (V)PABSD operates on signed 32-bit integers. The source operand can be an XMM register or a YMM register or a 128-bit memory location or 256-bit memory location. The destination operand can be an XMM or a YMM register. Both operands can be MMX register or XMM registers. VEX.256 encoded version: The first source operand is a YMM register or a 256-bit memory location. The destination operand is a YMM register. VEX.128 encoded version: The source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (255:128) of the corresponding YMM register destination are zeroed. 128-bit Legacy SSE version: The source operand can be an XMM register or a 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (255:128) of the corresponding YMM register destination are unmodified. Ref. # 319433-014 5-13
INSTRUCTION SET REFERENCE Operation PABSB with 128 bit operands: Unsigned DEST[7:0] ABS(SRC[7:.0]) Repeat operation for 2nd through 15th bytes Unsigned DEST[127:120] ABS(SRC[127:120]) VPABSB with 128 bit operands: Unsigned DEST[7:0] ABS(SRC[7:.0]) Repeat operation for 2nd through 15th bytes Unsigned DEST[127:120] ABS(SRC[127:120]) VPABSB with 256 bit operands: Unsigned DEST[7:0] ABS(SRC[7:.0]) Repeat operation for 2nd through 31st bytes Unsigned DEST[255:248] ABS(SRC[255:248]) PABSW with 128 bit operands: Unsigned DEST[15:0] ABS(SRC[15:0]) Repeat operation for 2nd through 7th 16-bit words Unsigned DEST[127:112] ABS(SRC[127:112]) VPABSW with 128 bit operands: Unsigned DEST[15:0] ABS(SRC[15:0]) Repeat operation for 2nd through 7th 16-bit words Unsigned DEST[127:112] ABS(SRC[127:112]) VPABSW with 256 bit operands: Unsigned DEST[15:0] ABS(SRC[15:0]) Repeat operation for 2nd through 15th 16-bit words Unsigned DEST[255:240] ABS(SRC[255:240]) PABSD with 128 bit operands: Unsigned DEST[31:0] ABS(SRC[31:0]) Repeat operation for 2nd through 3rd 32-bit double words Unsigned DEST[127:96] ABS(SRC[127:96]) VPABSD with 128 bit operands: Unsigned DEST[31:0] ABS(SRC[31:0]) Repeat operation for 2nd through 3rd 32-bit double words Unsigned DEST[127:96] ABS(SRC[127:96]) VPABSD with 256 bit operands: Unsigned DEST[31:0] ABS(SRC[31:0]) Repeat operation for 2nd through 7th 32-bit double words Unsigned DEST[255:224] ABS(SRC[255:224]) Intel C/C++ Compiler Intrinsic Equivalent PABSB: __m128i _mm_abs_epi8 (__m128i a) VPABSB: __m128i _mm_abs_epi8 (__m128i a) VPABSB: __m256i _mm256_abs_epi8 (__m256i a) 5-14 Ref. # 319433-014
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Intel® Architecture Instruction Se
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CONTENTS CHAPTER 1 INTEL® ADVANCED
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PANDN — Logical AND NOT . . . . .
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BZHI — Zero High Bits Starting wi
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TABLES 2-1 Rounding behavior of Zer
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FIGURES Figure 2-1. General Procedu
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INTEL® ADVANCED VECTOR EXTENSIONS
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APPLICATION PROGRAMMING MODEL Prior
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APPLICATION PROGRAMMING MODEL } and
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APPLICATION PROGRAMMING MODEL Scala
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APPLICATION PROGRAMMING MODEL x (mu
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APPLICATION PROGRAMMING MODEL Instr
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APPLICATION PROGRAMMING MODEL Table
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APPLICATION PROGRAMMING MODEL Excep
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APPLICATION PROGRAMMING MODEL 2.7.2
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APPLICATION PROGRAMMING MODEL Table
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Page 67 and 68: APPLICATION PROGRAMMING MODEL EAX[1
Page 69 and 70: APPLICATION PROGRAMMING MODEL EBX
Page 71 and 72: SYSTEM PROGRAMMING MODEL • Verify
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Page 75 and 76: SYSTEM PROGRAMMING MODEL 3.3 RESET
Page 77 and 78: INSTRUCTION FORMAT 4.1.1 VEX and th
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Page 81 and 82: INSTRUCTION FORMAT The VEX.vvvv fie
Page 83 and 84: INSTRUCTION FORMAT 4.1.8 The Third
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Page 91 and 92: INSTRUCTION SET REFERENCE MPSADBW
Page 93 and 94: INSTRUCTION SET REFERENCE SRC2_BYTE
Page 95 and 96: INSTRUCTION SET REFERENCE VMPSADBW
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Page 101 and 102: INSTRUCTION SET REFERENCE PACKSSWB/
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Page 105 and 106: INSTRUCTION SET REFERENCE PACKUSDW
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Page 111 and 112: INSTRUCTION SET REFERENCE PADDB/PAD
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Page 125 and 126: INSTRUCTION SET REFERENCE PAVGB/PAV
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Page 133 and 134: INSTRUCTION SET REFERENCE ELSE DEST
Page 135 and 136: INSTRUCTION SET REFERENCE Descripti
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Page 145 and 146: INSTRUCTION SET REFERENCE PHADDSW
Page 147 and 148: INSTRUCTION SET REFERENCE PHSUBW/PH
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INSTRUCTION SET REFERENCE DEST[95:8
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INSTRUCTION SET REFERENCE Operation
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INSTRUCTION SET REFERENCE PMADDUBSW
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INSTRUCTION SET REFERENCE VPMADDWD
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INSTRUCTION SET REFERENCE VEX.128 e
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INSTRUCTION SET REFERENCE DEST[255:
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INSTRUCTION SET REFERENCE VPMINUD (
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INSTRUCTION SET REFERENCE PMOVMSKB
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INSTRUCTION SET REFERENCE Opcode/ I
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INSTRUCTION SET REFERENCE VPMOVSXWQ
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INSTRUCTION SET REFERENCE PMOVZX
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INSTRUCTION SET REFERENCE Packed_Ze
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE temp13[31
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INSTRUCTION SET REFERENCE PMULHUW
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE PMULLW/PM
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INSTRUCTION SET REFERENCE Temp10[31
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INSTRUCTION SET REFERENCE PMULUDQ
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INSTRUCTION SET REFERENCE POR — B
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INSTRUCTION SET REFERENCE PSADBW
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INSTRUCTION SET REFERENCE PSHUFB
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INSTRUCTION SET REFERENCE PSHUFD
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INSTRUCTION SET REFERENCE PSHUFHW
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INSTRUCTION SET REFERENCE PSHUFLW
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INSTRUCTION SET REFERENCE PSIGNB/PS
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INSTRUCTION SET REFERENCE DEST[255.
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INSTRUCTION SET REFERENCE PSLLDQ
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INSTRUCTION SET REFERENCE PSLLW/PSL
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INSTRUCTION SET REFERENCE PSLLD (xm
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INSTRUCTION SET REFERENCE PSRAW/PSR
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INSTRUCTION SET REFERENCE COUNT 31
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INSTRUCTION SET REFERENCE PSRLDQ
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INSTRUCTION SET REFERENCE PSRLW/PSR
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INSTRUCTION SET REFERENCE FI; DEST[
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INSTRUCTION SET REFERENCE VPSRLQ (x
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE PSUBSB/PS
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INSTRUCTION SET REFERENCE PSUBUSB/P
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INSTRUCTION SET REFERENCE PUNPCKHBW
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INSTRUCTION SET REFERENCE VPUNPCKHW
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INSTRUCTION SET REFERENCE Instructi
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INSTRUCTION SET REFERENCE INTERLEAV
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INSTRUCTION SET REFERENCE VPUNPCKLD
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INSTRUCTION SET REFERENCE SIMD Floa
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INSTRUCTION SET REFERENCE VBROADCAS
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE VPBLENDD
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INSTRUCTION SET REFERENCE VPBROADCA
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INSTRUCTION SET REFERENCE VPERMPD
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INSTRUCTION SET REFERENCE VPERMQ
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INSTRUCTION SET REFERENCE VINSERTI1
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INSTRUCTION SET REFERENCE The secon
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INSTRUCTION SET REFERENCE VPSLLVD/V
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE VPSRAVD (
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INSTRUCTION SET REFERENCE VPSRLVD (
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE This page
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INSTRUCTION SET REFERENCE - FMA VFM
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INSTRUCTION SET REFERENCE - FMA For
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INSTRUCTION SET REFERENCE - FMA sou
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INSTRUCTION SET REFERENCE - FMA Int
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA } I
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INSTRUCTION SET REFERENCE - FMA ope
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INSTRUCTION SET REFERENCE - FMA VFN
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA Thi
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INSTRUCTION SET REFERENCE - VEX-ENC
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INTEL® TRANSACTIONAL SYNCHRONIZATI
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ADDITIONAL NEW INSTRUCTIONS -------
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ADDITIONAL NEW INSTRUCTIONS • If
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ADDITIONAL NEW INSTRUCTIONS ADCX
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ADDITIONAL NEW INSTRUCTIONS ADOX
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ADDITIONAL NEW INSTRUCTIONS Compati
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ADDITIONAL NEW INSTRUCTIONS Flags A
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ADDITIONAL NEW INSTRUCTIONS STAC—
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OPCODE MAP D The reg field of the M
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OPCODE MAP • A ModR/M byte is req
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OPCODE MAP A.2.5 Superscripts Utili
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OPCODE MAP Table A-2. One-byte Opco
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OPCODE MAP 0 1 2 3 4 5 6 7 Table A-
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OPCODE MAP 8 9 A B C D E F Table A-
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OPCODE MAP 0 Table A-4. Three-byte
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OPCODE MAP 0 66 1 66 2 66 3 4 66 5
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OPCODE MAP A.4 OPCODE EXTENSIONS FO
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OPCODE MAP Opcode Group Mod 7,6 pfx
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OPCODE MAP Table A-8 shows the map
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OPCODE MAP Table A-20 shows the opc
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OPCODE MAP This page was intentiona
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INSTRUCTION SUMMARY VEX.256 Encodin
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INSTRUCTION SUMMARY Note 3: It is e
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INSTRUCTION SUMMARY Table B-2. Prom
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INSTRUCTION SUMMARY Table B-3. VEX-
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INSTRUCTION SUMMARY Opcode Instruct
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SSE extensions flag . . . . . . . .
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SSE extensions CPUID flag . . . . .
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I-6 Ref. # 319433-014
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Intel® Architecture Instruction Set Extensions Programming Reference

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