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Intel® Architecture Instruction Set Extensions Programming Reference

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VEX.256<br />

Encoding<br />

VEX.128<br />

Encoding<br />

Table B-1. Promoted SSE/SSE2/SSE3/SSSE3/SSE4 <strong>Instruction</strong>s in AVX<br />

Group <strong>Instruction</strong> If No, Reason?<br />

no yes PADDUSB VI<br />

no yes PADDUSW VI<br />

no yes PMAXUB VI<br />

no yes PANDN VI<br />

no yes YY 0F EX PAVGB VI<br />

no yes PSRAW VI<br />

no yes PSRAD VI<br />

no yes PAVGW VI<br />

no yes PMULHUW VI<br />

no yes PMULHW VI<br />

yes yes CVTPD2DQ<br />

yes yes CVTTPD2DQ<br />

yes yes CVTDQ2PD<br />

yes yes MOVNTDQ VI<br />

no yes PSUBSB VI<br />

no yes PSUBSW VI<br />

no yes PMINSW VI<br />

no yes POR VI<br />

no yes PADDSB VI<br />

no yes PADDSW VI<br />

no yes PMAXSW VI<br />

no yes PXOR VI<br />

yes yes YY 0F FX LDDQU VI<br />

no yes PSLLW VI<br />

no yes PSLLD VI<br />

no yes PSLLQ VI<br />

no yes PMULUDQ VI<br />

no yes PMADDWD VI<br />

no yes PSADBW VI<br />

no yes MASKMOVDQU<br />

no yes PSUBB VI<br />

no yes PSUBW VI<br />

no yes PSUBD VI<br />

no yes PSUBQ VI<br />

no yes PADDB VI<br />

no yes PADDW VI<br />

no yes PADDD VI<br />

no yes SSSE3 PHADDW VI<br />

INSTRUCTION SUMMARY<br />

Ref. # 319433-014 B-5

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