Intel® Architecture Instruction Set Extensions Programming Reference

INSTRUCTION SET REFERENCE
DEST[79:64] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(DEST_BYTE5 - SRC_BYTE0)
TEMP1 ABS(DEST_BYTE6 - SRC_BYTE1)
TEMP2 ABS(DEST_BYTE7 - SRC_BYTE2)
TEMP3 ABS(DEST_BYTE8 - SRC_BYTE3)
DEST[95:80] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(DEST_BYTE6 - SRC_BYTE0)
TEMP1 ABS(DEST_BYTE7 - SRC_BYTE1)
TEMP2 ABS(DEST_BYTE8 - SRC_BYTE2)
TEMP3 ABS(DEST_BYTE9 - SRC_BYTE3)
DEST[111:96] TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 ABS(DEST_BYTE7 - SRC_BYTE0)
TEMP1 ABS(DEST_BYTE8 - SRC_BYTE1)
TEMP2 ABS(DEST_BYTE9 - SRC_BYTE2)
TEMP3 ABS(DEST_BYTE10 - SRC_BYTE3)
DEST[127:112] TEMP0 + TEMP1 + TEMP2 + TE
DEST[VLMAX:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
(V)MPSADBW: __m128i _mm_mpsadbw_epu8 (__m128i s1, __m128i s2, const int mask);
VMPSADBW: __m256i _mm256_mpsadbw_epu8 (__m256i s1, __m256i s2, const int mask);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4
5-12 Ref. # 319433-014