Intel® Architecture Instruction Set Extensions Programming Reference

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$Intel® Math Kernel Library (Intel® MKL) 11.0 Release Notes$

$Intel® Math Kernel Library 11.0 Support for Intel® Xeon Phi ...$

SRC1_BYTE5 SRC1[SRC1_OFFSET+47:SRC1_OFFSET+40] SRC1_BYTE6 SRC1[SRC1_OFFSET+55:SRC1_OFFSET+48] SRC1_BYTE7 SRC1[SRC1_OFFSET+63:SRC1_OFFSET+56] SRC1_BYTE8 SRC1[SRC1_OFFSET+71:SRC1_OFFSET+64] SRC1_BYTE9 SRC1[SRC1_OFFSET+79:SRC1_OFFSET+72] SRC1_BYTE10 SRC1[SRC1_OFFSET+87:SRC1_OFFSET+80] SRC2_BYTE0 SRC2[SRC2_OFFSET+7:SRC2_OFFSET] SRC2_BYTE1 SRC2[SRC2_OFFSET+15:SRC2_OFFSET+8] SRC2_BYTE2 SRC2[SRC2_OFFSET+23:SRC2_OFFSET+16] SRC2_BYTE3 SRC2[SRC2_OFFSET+31:SRC2_OFFSET+24] TEMP0 ABS(SRC1_BYTE0 - SRC2_BYTE0) TEMP1 ABS(SRC1_BYTE1 - SRC2_BYTE1) TEMP2 ABS(SRC1_BYTE2 - SRC2_BYTE2) TEMP3 ABS(SRC1_BYTE3 - SRC2_BYTE3) DEST[143:128] TEMP0 + TEMP1 + TEMP2 + TEMP3 TEMP0 ABS(SRC1_BYTE1 - SRC2_BYTE0) TEMP1 ABS(SRC1_BYTE2 - SRC2_BYTE1) TEMP2 ABS(SRC1_BYTE3 - SRC2_BYTE2) TEMP3 ABS(SRC1_BYTE4 - SRC2_BYTE3) DEST[159:144] TEMP0 + TEMP1 + TEMP2 + TEMP3 TEMP0 ABS(SRC1_BYTE2 - SRC2_BYTE0) TEMP1 ABS(SRC1_BYTE3 - SRC2_BYTE1) TEMP2 ABS(SRC1_BYTE4 - SRC2_BYTE2) TEMP3 ABS(SRC1_BYTE5 - SRC2_BYTE3) DEST[175:160] TEMP0 + TEMP1 + TEMP2 + TEMP3 TEMP0 ABS(SRC1_BYTE3 - SRC2_BYTE0) TEMP1 ABS(SRC1_BYTE4 - SRC2_BYTE1) TEMP2 ABS(SRC1_BYTE5 - SRC2_BYTE2) TEMP3 ABS(SRC1_BYTE6 - SRC2_BYTE3) DEST[191:176] TEMP0 + TEMP1 + TEMP2 + TEMP3 TEMP0 ABS(SRC1_BYTE4 - SRC2_BYTE0) TEMP1 ABS(SRC1_BYTE5 - SRC2_BYTE1) TEMP2 ABS(SRC1_BYTE6 - SRC2_BYTE2) TEMP3 ABS(SRC1_BYTE7 - SRC2_BYTE3) DEST[207:192] TEMP0 + TEMP1 + TEMP2 + TEMP3 TEMP0 ABS(SRC1_BYTE5 - SRC2_BYTE0) TEMP1 ABS(SRC1_BYTE6 - SRC2_BYTE1) TEMP2 ABS(SRC1_BYTE7 - SRC2_BYTE2) TEMP3 ABS(SRC1_BYTE8 - SRC2_BYTE3) DEST[223:208] TEMP0 + TEMP1 + TEMP2 + TEMP3 TEMP0 ABS(SRC1_BYTE6 - SRC2_BYTE0) TEMP1 ABS(SRC1_BYTE7 - SRC2_BYTE1) TEMP2 ABS(SRC1_BYTE8 - SRC2_BYTE2) TEMP3 ABS(SRC1_BYTE9 - SRC2_BYTE3) DEST[239:224] TEMP0 + TEMP1 + TEMP2 + TEMP3 TEMP0 ABS(SRC1_BYTE7 - SRC2_BYTE0) TEMP1 ABS(SRC1_BYTE8 - SRC2_BYTE1) TEMP2 ABS(SRC1_BYTE9 - SRC2_BYTE2) TEMP3 ABS(SRC1_BYTE10 - SRC2_BYTE3) DEST[255:240] TEMP0 + TEMP1 + TEMP2 + TEMP3 INSTRUCTION SET REFERENCE Ref. # 319433-014 5-9
INSTRUCTION SET REFERENCE VMPSADBW (VEX.128 encoded version) SRC2_OFFSET imm8[1:0]*32 SRC1_OFFSET imm8[2]*32 SRC1_BYTE0 SRC1[SRC1_OFFSET+7:SRC1_OFFSET] SRC1_BYTE1 SRC1[SRC1_OFFSET+15:SRC1_OFFSET+8] SRC1_BYTE2 SRC1[SRC1_OFFSET+23:SRC1_OFFSET+16] SRC1_BYTE3 SRC1[SRC1_OFFSET+31:SRC1_OFFSET+24] SRC1_BYTE4 SRC1[SRC1_OFFSET+39:SRC1_OFFSET+32] SRC1_BYTE5 SRC1[SRC1_OFFSET+47:SRC1_OFFSET+40] SRC1_BYTE6 SRC1[SRC1_OFFSET+55:SRC1_OFFSET+48] SRC1_BYTE7 SRC1[SRC1_OFFSET+63:SRC1_OFFSET+56] SRC1_BYTE8 SRC1[SRC1_OFFSET+71:SRC1_OFFSET+64] SRC1_BYTE9 SRC1[SRC1_OFFSET+79:SRC1_OFFSET+72] SRC1_BYTE10 SRC1[SRC1_OFFSET+87:SRC1_OFFSET+80] SRC2_BYTE0 SRC2[SRC2_OFFSET+7:SRC2_OFFSET] SRC2_BYTE1 SRC2[SRC2_OFFSET+15:SRC2_OFFSET+8] SRC2_BYTE2 SRC2[SRC2_OFFSET+23:SRC2_OFFSET+16] SRC2_BYTE3 SRC2[SRC2_OFFSET+31:SRC2_OFFSET+24] TEMP0 ABS(SRC1_BYTE0 - SRC2_BYTE0) TEMP1 ABS(SRC1_BYTE1 - SRC2_BYTE1) TEMP2 ABS(SRC1_BYTE2 - SRC2_BYTE2) TEMP3 ABS(SRC1_BYTE3 - SRC2_BYTE3) DEST[15:0] TEMP0 + TEMP1 + TEMP2 + TEMP3 TEMP0 ABS(SRC1_BYTE1 - SRC2_BYTE0) TEMP1 ABS(SRC1_BYTE2 - SRC2_BYTE1) TEMP2 ABS(SRC1_BYTE3 - SRC2_BYTE2) TEMP3 ABS(SRC1_BYTE4 - SRC2_BYTE3) DEST[31:16] TEMP0 + TEMP1 + TEMP2 + TEMP3 TEMP0 ABS(SRC1_BYTE2 - SRC2_BYTE0) TEMP1 ABS(SRC1_BYTE3 - SRC2_BYTE1) TEMP2 ABS(SRC1_BYTE4 - SRC2_BYTE2) TEMP3 ABS(SRC1_BYTE5 - SRC2_BYTE3) DEST[47:32] TEMP0 + TEMP1 + TEMP2 + TEMP3 TEMP0 ABS(SRC1_BYTE3 - SRC2_BYTE0) TEMP1 ABS(SRC1_BYTE4 - SRC2_BYTE1) TEMP2 ABS(SRC1_BYTE5 - SRC2_BYTE2) TEMP3 ABS(SRC1_BYTE6 - SRC2_BYTE3) DEST[63:48] TEMP0 + TEMP1 + TEMP2 + TEMP3 TEMP0 ABS(SRC1_BYTE4 - SRC2_BYTE0) TEMP1 ABS(SRC1_BYTE5 - SRC2_BYTE1) TEMP2 ABS(SRC1_BYTE6 - SRC2_BYTE2) TEMP3 ABS(SRC1_BYTE7 - SRC2_BYTE3) DEST[79:64] TEMP0 + TEMP1 + TEMP2 + TEMP3 TEMP0 ABS(SRC1_BYTE5 - SRC2_BYTE0) TEMP1 ABS(SRC1_BYTE6 - SRC2_BYTE1) TEMP2 ABS(SRC1_BYTE7 - SRC2_BYTE2) TEMP3 ABS(SRC1_BYTE8 - SRC2_BYTE3) DEST[95:80] TEMP0 + TEMP1 + TEMP2 + TEMP3 TEMP0 ABS(SRC1_BYTE6 - SRC2_BYTE0) TEMP1 ABS(SRC1_BYTE7 - SRC2_BYTE1) TEMP2 ABS(SRC1_BYTE8 - SRC2_BYTE2) TEMP3 ABS(SRC1_BYTE9 - SRC2_BYTE3) 5-10 Ref. # 319433-014
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Intel® Architecture Instruction Se
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CONTENTS CHAPTER 1 INTEL® ADVANCED
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PANDN — Logical AND NOT . . . . .
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BZHI — Zero High Bits Starting wi
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TABLES 2-1 Rounding behavior of Zer
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FIGURES Figure 2-1. General Procedu
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INTEL® ADVANCED VECTOR EXTENSIONS
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APPLICATION PROGRAMMING MODEL Prior
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APPLICATION PROGRAMMING MODEL } and
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APPLICATION PROGRAMMING MODEL Scala
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APPLICATION PROGRAMMING MODEL x (mu
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APPLICATION PROGRAMMING MODEL Instr
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APPLICATION PROGRAMMING MODEL Table
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APPLICATION PROGRAMMING MODEL Excep
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APPLICATION PROGRAMMING MODEL 2.7.2
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Page 43 and 44: APPLICATION PROGRAMMING MODEL 2.8.1
Page 45 and 46: APPLICATION PROGRAMMING MODEL Table
Page 53 and 54: APPLICATION PROGRAMMING MODEL EAX 3
Page 61 and 62: APPLICATION PROGRAMMING MODEL • T
Page 63 and 64: APPLICATION PROGRAMMING MODEL How B
Page 65 and 66: APPLICATION PROGRAMMING MODEL
Page 67 and 68: APPLICATION PROGRAMMING MODEL EAX[1
Page 69 and 70: APPLICATION PROGRAMMING MODEL EBX
Page 71 and 72: SYSTEM PROGRAMMING MODEL • Verify
Page 73 and 74: SYSTEM PROGRAMMING MODEL The proces
Page 75 and 76: SYSTEM PROGRAMMING MODEL 3.3 RESET
Page 77 and 78: INSTRUCTION FORMAT 4.1.1 VEX and th
Page 79 and 80: INSTRUCTION FORMAT (Bit Position) 7
Page 81 and 82: INSTRUCTION FORMAT The VEX.vvvv fie
Page 83 and 84: INSTRUCTION FORMAT 4.1.8 The Third
Page 85 and 86: INSTRUCTION FORMAT NOTES: 1. If Mod
Page 87 and 88: INSTRUCTION SET REFERENCE (V)ADDSD
Page 89 and 90: INSTRUCTION SET REFERENCE register
Page 91 and 92: INSTRUCTION SET REFERENCE MPSADBW
Page 93: INSTRUCTION SET REFERENCE SRC2_BYTE
Page 97 and 98: INSTRUCTION SET REFERENCE DEST[79:6
Page 99 and 100: INSTRUCTION SET REFERENCE Operation
Page 101 and 102: INSTRUCTION SET REFERENCE PACKSSWB/
Page 103 and 104: INSTRUCTION SET REFERENCE DEST[79:6
Page 105 and 106: INSTRUCTION SET REFERENCE PACKUSDW
Page 107 and 108: INSTRUCTION SET REFERENCE TMP[239:2
Page 109 and 110: INSTRUCTION SET REFERENCE DEST[119:
Page 111 and 112: INSTRUCTION SET REFERENCE PADDB/PAD
Page 113 and 114: INSTRUCTION SET REFERENCE PADDQ (Le
Page 115 and 116: INSTRUCTION SET REFERENCE PADDSB/PA
Page 117 and 118: INSTRUCTION SET REFERENCE PADDUSB/P
Page 119 and 120: INSTRUCTION SET REFERENCE PALIGNR
Page 121 and 122: INSTRUCTION SET REFERENCE PAND —
Page 123 and 124: INSTRUCTION SET REFERENCE PANDN —
Page 125 and 126: INSTRUCTION SET REFERENCE PAVGB/PAV
Page 127 and 128: INSTRUCTION SET REFERENCE PBLENDVB
Page 129 and 130: INSTRUCTION SET REFERENCE IF (MASK[
Page 131 and 132: INSTRUCTION SET REFERENCE PBLENDW
Page 133 and 134: INSTRUCTION SET REFERENCE ELSE DEST
Page 135 and 136: INSTRUCTION SET REFERENCE Descripti
Page 137 and 138: INSTRUCTION SET REFERENCE PCMPEQQ (
Page 139 and 140: INSTRUCTION SET REFERENCE Descripti
Page 141 and 142: INSTRUCTION SET REFERENCE Intel C/C
Page 143 and 144: INSTRUCTION SET REFERENCE Operation
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INSTRUCTION SET REFERENCE PHADDSW
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INSTRUCTION SET REFERENCE PHSUBW/PH
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INSTRUCTION SET REFERENCE DEST[95:8
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INSTRUCTION SET REFERENCE Operation
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INSTRUCTION SET REFERENCE PMADDUBSW
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INSTRUCTION SET REFERENCE VPMADDWD
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INSTRUCTION SET REFERENCE VEX.128 e
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INSTRUCTION SET REFERENCE DEST[255:
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INSTRUCTION SET REFERENCE VPMINUD (
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INSTRUCTION SET REFERENCE PMOVMSKB
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INSTRUCTION SET REFERENCE Opcode/ I
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INSTRUCTION SET REFERENCE VPMOVSXWQ
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INSTRUCTION SET REFERENCE PMOVZX
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INSTRUCTION SET REFERENCE Packed_Ze
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE temp13[31
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INSTRUCTION SET REFERENCE PMULHUW
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE PMULLW/PM
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INSTRUCTION SET REFERENCE Temp10[31
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INSTRUCTION SET REFERENCE PMULUDQ
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INSTRUCTION SET REFERENCE POR — B
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INSTRUCTION SET REFERENCE PSADBW
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INSTRUCTION SET REFERENCE PSHUFB
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INSTRUCTION SET REFERENCE PSHUFD
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INSTRUCTION SET REFERENCE PSHUFHW
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INSTRUCTION SET REFERENCE PSHUFLW
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INSTRUCTION SET REFERENCE PSIGNB/PS
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INSTRUCTION SET REFERENCE DEST[255.
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INSTRUCTION SET REFERENCE PSLLDQ
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INSTRUCTION SET REFERENCE PSLLW/PSL
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INSTRUCTION SET REFERENCE PSLLD (xm
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INSTRUCTION SET REFERENCE PSRAW/PSR
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INSTRUCTION SET REFERENCE COUNT 31
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INSTRUCTION SET REFERENCE PSRLDQ
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INSTRUCTION SET REFERENCE PSRLW/PSR
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INSTRUCTION SET REFERENCE FI; DEST[
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INSTRUCTION SET REFERENCE VPSRLQ (x
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE PSUBSB/PS
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INSTRUCTION SET REFERENCE PSUBUSB/P
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INSTRUCTION SET REFERENCE PUNPCKHBW
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INSTRUCTION SET REFERENCE VPUNPCKHW
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INSTRUCTION SET REFERENCE Instructi
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INSTRUCTION SET REFERENCE INTERLEAV
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INSTRUCTION SET REFERENCE VPUNPCKLD
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INSTRUCTION SET REFERENCE SIMD Floa
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INSTRUCTION SET REFERENCE VBROADCAS
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE VPBLENDD
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INSTRUCTION SET REFERENCE VPBROADCA
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INSTRUCTION SET REFERENCE VPERMPD
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INSTRUCTION SET REFERENCE VPERMQ
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INSTRUCTION SET REFERENCE VINSERTI1
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INSTRUCTION SET REFERENCE The secon
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INSTRUCTION SET REFERENCE VPSLLVD/V
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE VPSRAVD (
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INSTRUCTION SET REFERENCE VPSRLVD (
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE This page
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INSTRUCTION SET REFERENCE - FMA VFM
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INSTRUCTION SET REFERENCE - FMA For
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INSTRUCTION SET REFERENCE - FMA sou
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INSTRUCTION SET REFERENCE - FMA Int
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA } I
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INSTRUCTION SET REFERENCE - FMA ope
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INSTRUCTION SET REFERENCE - FMA VFN
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA Thi
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INSTRUCTION SET REFERENCE - VEX-ENC
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INTEL® TRANSACTIONAL SYNCHRONIZATI
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ADDITIONAL NEW INSTRUCTIONS -------
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ADDITIONAL NEW INSTRUCTIONS • If
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ADDITIONAL NEW INSTRUCTIONS ADCX
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ADDITIONAL NEW INSTRUCTIONS ADOX
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ADDITIONAL NEW INSTRUCTIONS Compati
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ADDITIONAL NEW INSTRUCTIONS Flags A
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ADDITIONAL NEW INSTRUCTIONS STAC—
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OPCODE MAP D The reg field of the M
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OPCODE MAP • A ModR/M byte is req
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OPCODE MAP A.2.5 Superscripts Utili
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OPCODE MAP Table A-2. One-byte Opco
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OPCODE MAP 0 1 2 3 4 5 6 7 Table A-
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OPCODE MAP 8 9 A B C D E F Table A-
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OPCODE MAP 0 Table A-4. Three-byte
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OPCODE MAP 0 66 1 66 2 66 3 4 66 5
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OPCODE MAP A.4 OPCODE EXTENSIONS FO
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OPCODE MAP Opcode Group Mod 7,6 pfx
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OPCODE MAP Table A-8 shows the map
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OPCODE MAP Table A-20 shows the opc
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OPCODE MAP This page was intentiona
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INSTRUCTION SUMMARY VEX.256 Encodin
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INSTRUCTION SUMMARY Note 3: It is e
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INSTRUCTION SUMMARY Table B-2. Prom
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INSTRUCTION SUMMARY Table B-3. VEX-
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INSTRUCTION SUMMARY Opcode Instruct
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SSE extensions flag . . . . . . . .
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SSE extensions CPUID flag . . . . .
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I-6 Ref. # 319433-014
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Intel® Architecture Instruction Set Extensions Programming Reference

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