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Intel® Architecture Instruction Set Extensions Programming Reference

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INSTRUCTION SET REFERENCE - FMA<br />

source operand, performs rounding and stores the resulting four or eight packed single-precision floating-point<br />

values to the destination operand (first source operand).<br />

VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in<br />

reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a<br />

YMM register or a 256-bit memory location and encoded in rm_field.<br />

VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in<br />

reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a<br />

XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination<br />

register are zeroed.<br />

Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the<br />

opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations<br />

involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction<br />

column. See also Section 2.3.1, “FMA <strong>Instruction</strong> Operand Order and Arithmetic Behavior”<br />

Operation<br />

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations<br />

with infinite precision inputs and outputs (no rounding).<br />

VFMADD132PS DEST, SRC2, SRC3<br />

IF (VEX.128) THEN<br />

MAXVL =4<br />

ELSEIF (VEX.256)<br />

MAXVL = 8<br />

FI<br />

For i = 0 to MAXVL-1 {<br />

n = 32*i;<br />

DEST[n+31:n] RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] + SRC2[n+31:n])<br />

}<br />

IF (VEX.128) THEN<br />

DEST[VLMAX-1:128] 0<br />

FI<br />

VFMADD213PS DEST, SRC2, SRC3<br />

IF (VEX.128) THEN<br />

MAXVL =4<br />

ELSEIF (VEX.256)<br />

MAXVL = 8<br />

FI<br />

For i = 0 to MAXVL-1 {<br />

n = 32*i;<br />

DEST[n+31:n] RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] + SRC3[n+31:n])<br />

}<br />

IF (VEX.128) THEN<br />

DEST[VLMAX-1:128] 0<br />

FI<br />

VFMADD231PS DEST, SRC2, SRC3<br />

IF (VEX.128) THEN<br />

MAXVL =4<br />

ELSEIF (VEX.256)<br />

MAXVL = 8<br />

FI<br />

For i = 0 to MAXVL-1 {<br />

n = 32*i;<br />

6-6 Ref. # 319433-014

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