Intel® Architecture Instruction Set Extensions Programming Reference

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$Intel® Math Kernel Library (Intel® MKL) 11.0 Release Notes$

$Intel® Math Kernel Library 11.0 Support for Intel® Xeon Phi ...$

8 9 A B C D E F Table A-3. Two-byte Opcode Map: 88H — FFH (First Byte is 0FH) * pfx 8 9 A B C D E F F3 66 F3 F2 66 F3 F2 66 F2 OPCODE MAP Jccf64 , Jz - Long-displacement jump on condition S NS P/PE NP/PO L/NGE NL/GE LE/NG NLE/G SETcc, Eb - Byte <strong>Set</strong> on condition S NS P/PE NP/PO L/NGE NL/GE LE/NG NLE/G PUSH d64 GS JMPE (reserved for emulator on IPF) POPCNT Gv, Ev RAX/EAX/ R8/R8D psubusb Pq, Qq vpsubusb Vx, Hx, Wx psubsb Pq, Qq vpsubsb Vx, Hx, Wx psubb Pq, Qq vpsubb Vx, Hx, Wx POP d64 GS Grp 101A Invalid Opcode1B RCX/ECX/ R9/R9D psubusw Pq, Qq vpsubusw Vx, Hx, Wx psubsw Pq, Qq vpsubsw Vx, Hx, Wx psubw Pq, Qq vpsubw Vx, Hx, Wx RSM BTS Ev, Gv Grp 8 1A Ev, Ib RDX/EDX/ R10/R10D pminub Pq, Qq vpminub Vx, Hx, Wx pminsw Pq, Qq vpminsw Vx, Hx, Wx psubd Pq, Qq vpsubd Vx, Hx, Wx BTC Ev, Gv RBX/EBX/ R11/R11D pand Pq, Qq vpand Vx, Hx, Wx por Pq, Qq vpor Vx, Hx, Wx psubq Pq, Qq vpsubq Vx, Hx, Wx SHRD Ev, Gv, Ib SHRD Ev, Gv, CL (Grp 15 1A ) 1C Ref. # 319433-014 A-13 BSWAP BSF Gv, Ev TZCNT Gv, Ev RSP/ESP/ R12/R12D paddusb Pq, Qq vpaddusb Vx, Hx, Wx paddsb Pq, Qq vpaddsb Vx, Hx, Wx paddb Pq, Qq vpaddb Vx, Hx, Wx BSR Gv, Ev LZCNT Gv, Ev RBP/EBP/ R13/R13D paddusw Pq, Qq vpaddusw Vx, Hx, Wx paddsw Pq, Qq vpaddsw Vx, Hx, Wx paddw Pq, Qq vpaddw Vx, Hx, Wx IMUL Gv, Ev MOVSX Gv, Eb Gv, Ew RSI/ESI/ R14/R14D pmaxub Pq, Qq vpmaxub Vx, Hx, Wx pmaxsw Pq, Qq vpmaxsw Vx, Hx, Wx paddd Pq, Qq vpaddd Vx, Hx, Wx NOTES: * All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations. RDI/EDI/ R15/R15D pandn Pq, Qq vpandn Vx, Hx, Wx pxor Pq, Qq vpxor Vx, Hx, Wx
OPCODE MAP 0 Table A-4. Three-byte Opcode Map: 00H — F7H (First Two Bytes are 0F 38H) * pfx 0 1 2 3 4 5 6 7 66 1 66 2 66 3 66 4 66 5 6 7 8 66 9 66 A 66 B 66 C D E F 66 F3 F2 66 & F2 pshufb Pq, Qq vpshufb Vx, Hx, Wx pblendvb Vdq, Wdq vpmovsxbw Vx, Ux/Mq vpmovzxbw Vx, Ux/Mq vpmulld Vx, Hx, Wx INVEPT Gy, Mdq vgatherdd/q v Vx,Hx,Wx MOVBE Gy, My MOVBE Gw, Mw CRC32 Gd, Eb CRC32 Gd, Eb phaddw Pq, Qq vphaddw Vx, Hx, Wx vpmovsxbd Vx, Ux/Md vpmovzxbd Vx, Ux/Md vphminposuw Vdq, Wdq INVVPID Gy, Mdq vgatherqd/q v Vx,Hx,Wx MOVBE My, Gy MOVBE Mw, Gw CRC32 Gd, Ey CRC32 Gd, Ew phaddd Pq, Qq vphaddd Vx, Hx, Wx vpmovsxbq Vx, Ux/Mw vpmovzxbq Vx, Ux/Mw INVPCID Gy, Mdq vgatherdps/d v Vx,Hx,Wx ANDN v Gy, By, Ey phaddsw Pq, Qq vphaddsw Vx, Hx, Wx vcvtph2ps v Vx, Wx, Ib vpmovsxwd Vx, Ux/Mq vpmovzxwd Vx, Ux/Mq vgatherqps/d v Vx,Hx,Wx Grp 17 1A pmaddubsw Pq, Qq vpmaddubsw Vx, Hx, Wx blendvps Vdq, Wdq vpmovsxwq Vx, Ux/Md vpmovzxwq Vx, Ux/Md A-14 Ref. # 319433-014 phsubw Pq, Qq vphsubw Vx, Hx, Wx blendvpd Vdq, Wdq vpmovsxdq Vx, Ux/Mq vpmovzxdq Vx, Ux/Mq vpsrlvd/q v Vx, Hx, Wx BZHI v Gy, Ey, By PEXT v Gy, By, Ey PDEP v Gy, By, Ey phsubd Pq, Qq vphsubd Vx, Hx, Wx vpermps v Vqq, Hqq, Wqq vpermd v Vqq, Hqq, Wqq vpsravd v Vx, Hx, Wx vfmaddsub132ps/d v Vx,Hx,Wx vfmaddsub213ps/d v Vx,Hx,Wx vfmaddsub231ps/d v Vx,Hx,Wx ADCX Gy, Ey ADOX Gy, Ey MULX v By,Gy,rDX,Ey phsubsw Pq, Qq vphsubsw Vx, Hx, Wx vptest Vx, Wx vpcmpgtq Vx, Hx, Wx vpsllvd/q v Vx, Hx, Wx vfmsubadd132ps/d v Vx,Hx,Wx vfmsubadd213ps/d v Vx,Hx,Wx vfmsubadd231ps/d v Vx,Hx,Wx BEXTR v Gy, Ey, By SHLX v Gy, Ey, By SARX v Gy, Ey, By SHRX v Gy, Ey, By
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Intel® Architecture Instruction Se
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CONTENTS CHAPTER 1 INTEL® ADVANCED
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PANDN — Logical AND NOT . . . . .
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BZHI — Zero High Bits Starting wi
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TABLES 2-1 Rounding behavior of Zer
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FIGURES Figure 2-1. General Procedu
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INTEL® ADVANCED VECTOR EXTENSIONS
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APPLICATION PROGRAMMING MODEL Prior
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APPLICATION PROGRAMMING MODEL } and
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APPLICATION PROGRAMMING MODEL Scala
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APPLICATION PROGRAMMING MODEL x (mu
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APPLICATION PROGRAMMING MODEL Instr
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APPLICATION PROGRAMMING MODEL Table
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APPLICATION PROGRAMMING MODEL Excep
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APPLICATION PROGRAMMING MODEL 2.7.2
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APPLICATION PROGRAMMING MODEL EAX 3
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APPLICATION PROGRAMMING MODEL • T
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APPLICATION PROGRAMMING MODEL How B
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APPLICATION PROGRAMMING MODEL
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APPLICATION PROGRAMMING MODEL EAX[1
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APPLICATION PROGRAMMING MODEL EBX
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SYSTEM PROGRAMMING MODEL • Verify
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SYSTEM PROGRAMMING MODEL The proces
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SYSTEM PROGRAMMING MODEL 3.3 RESET
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INSTRUCTION FORMAT 4.1.1 VEX and th
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INSTRUCTION FORMAT (Bit Position) 7
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INSTRUCTION FORMAT The VEX.vvvv fie
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INSTRUCTION FORMAT 4.1.8 The Third
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INSTRUCTION FORMAT NOTES: 1. If Mod
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INSTRUCTION SET REFERENCE (V)ADDSD
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INSTRUCTION SET REFERENCE register
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INSTRUCTION SET REFERENCE MPSADBW
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INSTRUCTION SET REFERENCE SRC2_BYTE
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INSTRUCTION SET REFERENCE VMPSADBW
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INSTRUCTION SET REFERENCE DEST[79:6
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INSTRUCTION SET REFERENCE Operation
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INSTRUCTION SET REFERENCE PACKSSWB/
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INSTRUCTION SET REFERENCE PACKUSDW
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INSTRUCTION SET REFERENCE TMP[239:2
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INSTRUCTION SET REFERENCE DEST[119:
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INSTRUCTION SET REFERENCE PADDB/PAD
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INSTRUCTION SET REFERENCE PADDQ (Le
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INSTRUCTION SET REFERENCE PADDSB/PA
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INSTRUCTION SET REFERENCE PADDUSB/P
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INSTRUCTION SET REFERENCE PALIGNR
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INSTRUCTION SET REFERENCE PAND —
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INSTRUCTION SET REFERENCE PANDN —
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INSTRUCTION SET REFERENCE PAVGB/PAV
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INSTRUCTION SET REFERENCE PBLENDVB
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INSTRUCTION SET REFERENCE IF (MASK[
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INSTRUCTION SET REFERENCE PBLENDW
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INSTRUCTION SET REFERENCE ELSE DEST
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INSTRUCTION SET REFERENCE Descripti
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INSTRUCTION SET REFERENCE PCMPEQQ (
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INSTRUCTION SET REFERENCE Intel C/C
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INSTRUCTION SET REFERENCE PHADDSW
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INSTRUCTION SET REFERENCE PHSUBW/PH
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INSTRUCTION SET REFERENCE PMADDUBSW
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INSTRUCTION SET REFERENCE VPMADDWD
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INSTRUCTION SET REFERENCE VEX.128 e
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INSTRUCTION SET REFERENCE VPMINUD (
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INSTRUCTION SET REFERENCE PMOVMSKB
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INSTRUCTION SET REFERENCE Opcode/ I
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INSTRUCTION SET REFERENCE VPMOVSXWQ
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INSTRUCTION SET REFERENCE PMOVZX
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INSTRUCTION SET REFERENCE Packed_Ze
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE temp13[31
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INSTRUCTION SET REFERENCE PMULHUW
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INSTRUCTION SET REFERENCE PMULLW/PM
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INSTRUCTION SET REFERENCE Temp10[31
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INSTRUCTION SET REFERENCE PMULUDQ
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INSTRUCTION SET REFERENCE POR — B
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INSTRUCTION SET REFERENCE PSADBW
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INSTRUCTION SET REFERENCE PSHUFB
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INSTRUCTION SET REFERENCE PSHUFD
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INSTRUCTION SET REFERENCE PSHUFHW
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INSTRUCTION SET REFERENCE PSHUFLW
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INSTRUCTION SET REFERENCE PSIGNB/PS
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INSTRUCTION SET REFERENCE DEST[255.
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INSTRUCTION SET REFERENCE PSLLDQ
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INSTRUCTION SET REFERENCE PSLLW/PSL
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INSTRUCTION SET REFERENCE PSLLD (xm
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INSTRUCTION SET REFERENCE PSRAW/PSR
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INSTRUCTION SET REFERENCE COUNT 31
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INSTRUCTION SET REFERENCE PSRLDQ
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INSTRUCTION SET REFERENCE PSRLW/PSR
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INSTRUCTION SET REFERENCE FI; DEST[
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INSTRUCTION SET REFERENCE VPSRLQ (x
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INSTRUCTION SET REFERENCE PSUBSB/PS
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INSTRUCTION SET REFERENCE PSUBUSB/P
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INSTRUCTION SET REFERENCE PUNPCKHBW
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INSTRUCTION SET REFERENCE VPUNPCKHW
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INSTRUCTION SET REFERENCE Instructi
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INSTRUCTION SET REFERENCE INTERLEAV
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INSTRUCTION SET REFERENCE VPUNPCKLD
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INSTRUCTION SET REFERENCE SIMD Floa
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INSTRUCTION SET REFERENCE VBROADCAS
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INSTRUCTION SET REFERENCE VPBLENDD
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INSTRUCTION SET REFERENCE VPBROADCA
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INSTRUCTION SET REFERENCE VPERMPD
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INSTRUCTION SET REFERENCE VPERMQ
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INSTRUCTION SET REFERENCE VINSERTI1
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INSTRUCTION SET REFERENCE The secon
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INSTRUCTION SET REFERENCE VPSLLVD/V
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INSTRUCTION SET REFERENCE Other Exc
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INSTRUCTION SET REFERENCE VPSRAVD (
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INSTRUCTION SET REFERENCE VPSRLVD (
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VGATHERDP
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INSTRUCTION SET REFERENCE VGATHERQP
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE VPGATHERD
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INSTRUCTION SET REFERENCE VPGATHERQ
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INSTRUCTION SET REFERENCE This page
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INSTRUCTION SET REFERENCE - FMA VFM
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INSTRUCTION SET REFERENCE - FMA For
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INSTRUCTION SET REFERENCE - FMA sou
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INSTRUCTION SET REFERENCE - FMA Int
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA the
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INSTRUCTION SET REFERENCE - FMA } I
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INSTRUCTION SET REFERENCE - FMA ope
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INSTRUCTION SET REFERENCE - FMA VFN
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA VEX
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INSTRUCTION SET REFERENCE - FMA Thi
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INSTRUCTION SET REFERENCE - VEX-ENC
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Page 381 and 382: INSTRUCTION SET REFERENCE - VEX-ENC
Page 387 and 388: INTEL® TRANSACTIONAL SYNCHRONIZATI
Page 407 and 408: ADDITIONAL NEW INSTRUCTIONS -------
Page 409 and 410: ADDITIONAL NEW INSTRUCTIONS • If
Page 411 and 412: ADDITIONAL NEW INSTRUCTIONS ADCX
Page 413 and 414: ADDITIONAL NEW INSTRUCTIONS ADOX
Page 415 and 416: ADDITIONAL NEW INSTRUCTIONS Compati
Page 417 and 418: ADDITIONAL NEW INSTRUCTIONS Flags A
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Page 421 and 422: OPCODE MAP D The reg field of the M
Page 423 and 424: OPCODE MAP • A ModR/M byte is req
Page 425 and 426: OPCODE MAP A.2.5 Superscripts Utili
Page 427 and 428: OPCODE MAP Table A-2. One-byte Opco
Page 429 and 430: OPCODE MAP 0 1 2 3 4 5 6 7 Table A-
Page 431: OPCODE MAP 8 9 A B C D E F Table A-
Page 435 and 436: OPCODE MAP 0 66 1 66 2 66 3 4 66 5
Page 437 and 438: OPCODE MAP A.4 OPCODE EXTENSIONS FO
Page 439 and 440: OPCODE MAP Opcode Group Mod 7,6 pfx
Page 441 and 442: OPCODE MAP Table A-8 shows the map
Page 447 and 448: OPCODE MAP Table A-20 shows the opc
Page 449 and 450: OPCODE MAP This page was intentiona
Page 451 and 452: INSTRUCTION SUMMARY VEX.256 Encodin
Page 457 and 458: INSTRUCTION SUMMARY Note 3: It is e
Page 459 and 460: INSTRUCTION SUMMARY Table B-2. Prom
Page 461 and 462: INSTRUCTION SUMMARY Table B-3. VEX-
Page 463 and 464: INSTRUCTION SUMMARY Opcode Instruct
Page 473 and 474: SSE extensions flag . . . . . . . .
Page 475 and 476: SSE extensions CPUID flag . . . . .
Page 477: I-6 Ref. # 319433-014
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